/*
 * Reset, vectors and interrupt entries of the PIC32MZ bare-metal fixture (MIPS32r2: the
 * microAptiv UP of the MZ EC, the M-Class core of the MZ EF). The CPU starts at 0xBFC00000
 * with BEV and ERL set, in MIPS32 as DEVCFG0.BOOTISA says (FRM Section 50.23). This sets up the
 * stack, copies .data, clears .bss, places EBase at 0x9D000000 and leaves BEV and ERL for
 * main(). The controller presents each vector's offset from EBase that its OFFx register holds
 * (DS60001108H 8.5.2): main() writes OFF000 and OFF009 with the handlers below.
 */
        .set noreorder
        .set noat
        .section .reset, "ax"
        .globl _reset
_reset:
        la      $sp, _stack
        la      $t0, _data_load
        la      $t1, _data
        la      $t2, _edata
1:      beq     $t1, $t2, 2f
        nop
        lw      $t3, 0($t0)
        sw      $t3, 0($t1)
        addiu   $t0, 4
        b       1b
        addiu   $t1, 4
2:      la      $t1, _bss
        la      $t2, _ebss
3:      beq     $t1, $t2, 4f
        nop
        sw      $zero, 0($t1)
        b       3b
        addiu   $t1, 4
4:      la      $t0, 0x9D000000
        mtc0    $t0, $15, 1             /* EBase */
        li      $t0, 0x00800000
        mtc0    $t0, $13                /* Cause.IV */
        mtc0    $zero, $12              /* Status: BEV, ERL, EXL clear; IPL 0; IE off */
        ehb
        la      $t0, main
        jr      $t0
        nop

/*
 * The configuration words: MICROCHIP_MZ_STARTER_KIT.hex's (chipKIT32/PIC32-avrdude-
 * bootloader) -- a 24 MHz clock (EC) /3 x50 /2 = 200 MHz from the system PLL, BOOTISA MIPS32,
 * the watchdog and the deadman timer off -- with DEVCFG3.IOL1WAY 1 (the erased value).
 * DEVCFG3 is lowest (DS60001320H Registers 34-3 to 34-6).
 */
        .section .config, "a"
        .word   0xbeffffff              /* DEVCFG3: IOL1WAY 1 */
        .word   0xfff9b11a              /* DEVCFG2: FPLLIDIV /3, FPLLRNG 5-10, POSC, x50, /2 */
        .word   0x03743839              /* DEVCFG1: FNOSC SPLL, POSCMOD EC, FWDTEN 0, FDMTEN 0 */
        .word   0xfffff7f7              /* DEVCFG0: BOOTISA MIPS32 */

        .section .vectors, "ax"
        .org    0x180                   /* general exception */
        la      $k0, exc_handler
        jr      $k0
        nop
        .org    0x200

        .text
/* The core timer's: priority 7, on shadow set 1 (PRISS.PRI7SS); the stack pointer comes over
 * from the interrupted set (RDPGPR), nothing else needs saving. */
        .globl  ct_isr
ct_isr:
        .word   0x41400000 | (29 << 16) | (29 << 11)   /* rdpgpr $sp, $sp */
        la      $k0, ct_seen_sp
        sw      $sp, 0($k0)
        addiu   $sp, $sp, -16
        la      $t0, ct_handler
        jalr    $t0
        nop
        addiu   $sp, $sp, 16
        eret
        nop

/* Every other: on the normal registers, saving what the C handler may clobber. */
        .macro  isr name, handler
        .globl  \name
\name:
        addiu   $sp, $sp, -96
        sw      $at, 4($sp)
        sw      $v0, 8($sp)
        sw      $v1, 12($sp)
        sw      $a0, 16($sp)
        sw      $a1, 20($sp)
        sw      $a2, 24($sp)
        sw      $a3, 28($sp)
        sw      $t0, 32($sp)
        sw      $t1, 36($sp)
        sw      $t2, 40($sp)
        sw      $t3, 44($sp)
        sw      $t4, 48($sp)
        sw      $t5, 52($sp)
        sw      $t6, 56($sp)
        sw      $t7, 60($sp)
        sw      $t8, 64($sp)
        sw      $t9, 68($sp)
        sw      $ra, 72($sp)
        mfhi    $k0
        sw      $k0, 76($sp)
        mflo    $k0
        sw      $k0, 80($sp)
        la      $t0, \handler
        jalr    $t0
        nop
        lw      $k0, 80($sp)
        mtlo    $k0
        lw      $k0, 76($sp)
        mthi    $k0
        lw      $at, 4($sp)
        lw      $v0, 8($sp)
        lw      $v1, 12($sp)
        lw      $a0, 16($sp)
        lw      $a1, 20($sp)
        lw      $a2, 24($sp)
        lw      $a3, 28($sp)
        lw      $t0, 32($sp)
        lw      $t1, 36($sp)
        lw      $t2, 40($sp)
        lw      $t3, 44($sp)
        lw      $t4, 48($sp)
        lw      $t5, 52($sp)
        lw      $t6, 56($sp)
        lw      $t7, 60($sp)
        lw      $t8, 64($sp)
        lw      $t9, 68($sp)
        lw      $ra, 72($sp)
        addiu   $sp, $sp, 96
        eret
        nop
        .endm

        isr     t2_isr, t2_handler
        isr     cn_isr, cn_handler

/*
 * sqrt(2) on the FPU, as a 64-bit double in FR=1 mode (the MZ EF's FPU: DS60001320H 3.3;
 * the caller has set Status.CU1 and FR): returns its bits, high word in $v1.
 */
        .globl  fpu_sqrt2
        .set    push
        .set    hardfloat
        .set    fp=64
fpu_sqrt2:
        lui     $t0, 0x4000             /* 2.0 = 0x40000000_00000000 */
        mtc1    $zero, $f2
        mthc1   $t0, $f2
        sqrt.d  $f0, $f2
        mfc1    $v0, $f0
        mfhc1   $v1, $f0
        jr      $ra
        nop
        .set    pop