/*
 * Reset, vectors and the interrupt entries of the PIC32MX1xx/2xx bare-metal fixture
 * (MIPS32r2, the M4K with no shadow register set: DS60001168L "7.0 Interrupt Controller",
 * one register set, so every handler saves what it clobbers). The CPU starts at 0xBFC00000
 * with BEV and ERL set (PIC32 FRM Section 2); this sets up the stack, copies .data, clears
 * .bss, places EBase at 0x9D000000, picks 32-byte vector spacing and vectored interrupts
 * (IntCtl.VS, Cause.IV), and leaves BEV and ERL for main().
 */
        .set noreorder
        .set noat
        .section .reset, "ax"
        .globl _reset
_reset:
        la      $sp, _stack
        la      $t0, _data_load
        la      $t1, _data
        la      $t2, _edata
1:      beq     $t1, $t2, 2f
        nop
        lw      $t3, 0($t0)
        sw      $t3, 0($t1)
        addiu   $t0, 4
        b       1b
        addiu   $t1, 4
2:      la      $t1, _bss
        la      $t2, _ebss
3:      beq     $t1, $t2, 4f
        nop
        sw      $zero, 0($t1)
        b       3b
        addiu   $t1, 4
4:      la      $t0, 0x9D000000
        mtc0    $t0, $15, 1             /* EBase */
        li      $t0, 0x20
        mtc0    $t0, $12, 1             /* IntCtl.VS = 1: 32 bytes */
        li      $t0, 0x00800000
        mtc0    $t0, $13                /* Cause.IV */
        mtc0    $zero, $12              /* Status: BEV, ERL, EXL clear; IPL 0; IE off */
        ehb
        la      $t0, main
        jr      $t0
        nop

/*
 * The configuration words (DS60001168L Registers 27-1..27-4): chipKIT_Pi.hex's -- an 8 MHz
 * crystal (HS) through the PLL /2 x20 /2 = 40 MHz, PBCLK /1, the watchdog off -- but DEVCFG3
 * erased, so IOL1WAY is 1: CFGCON.IOLOCK, once set, stays set. DEVCFG3 is lowest.
 */
        .section .config, "a"
        .word   0xffffffff              /* DEVCFG3: IOL1WAY 1 */
        .word   0xfff979d9              /* DEVCFG2: FPLLIDIV /2, FPLLMUL x20, FPLLODIV /2 */
        .word   0xff6a0e5b              /* DEVCFG1: FNOSC POSC+PLL, POSCMOD HS, FPBDIV /1, FWDTEN 0 */
        .word   0x7ffffffb              /* DEVCFG0 */

/* Each vector saves the caller-saved registers and calls its C handler (no shadow set). */
        .macro  isr name, handler
\name:
        addiu   $sp, $sp, -96
        sw      $at, 4($sp)
        sw      $v0, 8($sp)
        sw      $v1, 12($sp)
        sw      $a0, 16($sp)
        sw      $a1, 20($sp)
        sw      $a2, 24($sp)
        sw      $a3, 28($sp)
        sw      $t0, 32($sp)
        sw      $t1, 36($sp)
        sw      $t2, 40($sp)
        sw      $t3, 44($sp)
        sw      $t4, 48($sp)
        sw      $t5, 52($sp)
        sw      $t6, 56($sp)
        sw      $t7, 60($sp)
        sw      $t8, 64($sp)
        sw      $t9, 68($sp)
        sw      $ra, 72($sp)
        mfhi    $k0
        sw      $k0, 76($sp)
        mflo    $k0
        sw      $k0, 80($sp)
        la      $t0, \handler
        jalr    $t0
        nop
        lw      $k0, 80($sp)
        mtlo    $k0
        lw      $k0, 76($sp)
        mthi    $k0
        lw      $at, 4($sp)
        lw      $v0, 8($sp)
        lw      $v1, 12($sp)
        lw      $a0, 16($sp)
        lw      $a1, 20($sp)
        lw      $a2, 24($sp)
        lw      $a3, 28($sp)
        lw      $t0, 32($sp)
        lw      $t1, 36($sp)
        lw      $t2, 40($sp)
        lw      $t3, 44($sp)
        lw      $t4, 48($sp)
        lw      $t5, 52($sp)
        lw      $t6, 56($sp)
        lw      $t7, 60($sp)
        lw      $t8, 64($sp)
        lw      $t9, 68($sp)
        lw      $ra, 72($sp)
        addiu   $sp, $sp, 96
        eret
        nop
        .endm

        .section .vectors, "ax"
        .org    0x180                   /* general exception */
        la      $k0, exc_handler
        jr      $k0
        nop
        /* The MX1xx/2xx's vectors (DS60001168L Table 7-1): core timer 0, Timer2 8, INT4 19,
         * change notice 34. */
        .org    0x200 + 0 * 32
        la      $k0, ct_isr
        jr      $k0
        nop
        .org    0x200 + 8 * 32
        la      $k0, t2_isr
        jr      $k0
        nop
        .org    0x200 + 19 * 32
        la      $k0, int4_isr
        jr      $k0
        nop
        .org    0x200 + 34 * 32
        la      $k0, cn_isr
        jr      $k0
        nop
        .org    0x200 + 64 * 32

        .text
        isr     ct_isr, ct_handler
        isr     t2_isr, t2_handler
        isr     int4_isr, int4_handler
        isr     cn_isr, cn_handler