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flowrs-engine/crates/flowrs-sim/data/timebase/measured.json
flowRS 2b6f30d348 flowRS engine, cut from flowRS f907e0756a7c 
Built alone from an empty CARGO_HOME, its tests passed, and flowrsc checked, ran and exported a
document from the conformance corpus; the export built alone.

Co-Authored-By: Claude Opus 5.5 <[email protected]>
2026-11-10 08:54:33 -05:00

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[
{
"engine": "avr8js",
"version": "0.21.1-flowrs",
"source": "Microchip, AVR Instruction Set Manual, DS40002198B (2021), Tables 5-2 to 5-5, AVRe column",
"not_covered": [
"the AVRxt and AVRxm cores (megaAVR 0-series, AVR Dx, XMEGA), which this measures on the classic core only",
"parts with a 22-bit program counter (over 128 KB of flash), whose calls and returns take one cycle more",
"interrupt entry and exit, sleep and the SPM instruction"
],
"samples": [
{
"instruction": "NOP",
"table": 1,
"measured": 1
},
{
"instruction": "LDI r16, 1",
"table": 1,
"measured": 1
},
{
"instruction": "MOV r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "MOVW r16, r18",
"table": 1,
"measured": 1
},
{
"instruction": "ADD r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "ADC r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "SUB r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "SUBI r16, 1",
"table": 1,
"measured": 1
},
{
"instruction": "AND r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "ANDI r16, 1",
"table": 1,
"measured": 1
},
{
"instruction": "OR r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "EOR r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "COM r16",
"table": 1,
"measured": 1
},
{
"instruction": "NEG r16",
"table": 1,
"measured": 1
},
{
"instruction": "INC r16",
"table": 1,
"measured": 1
},
{
"instruction": "DEC r16",
"table": 1,
"measured": 1
},
{
"instruction": "LSR r16",
"table": 1,
"measured": 1
},
{
"instruction": "ASR r16",
"table": 1,
"measured": 1
},
{
"instruction": "ROR r16",
"table": 1,
"measured": 1
},
{
"instruction": "SWAP r16",
"table": 1,
"measured": 1
},
{
"instruction": "ADIW r24, 1",
"table": 2,
"measured": 2
},
{
"instruction": "SBIW r24, 1",
"table": 2,
"measured": 2
},
{
"instruction": "MUL r16, r17",
"table": 2,
"measured": 2
},
{
"instruction": "CP r16, r17",
"table": 1,
"measured": 1
},
{
"instruction": "CPI r16, 1",
"table": 1,
"measured": 1
},
{
"instruction": "RJMP .+0",
"table": 2,
"measured": 2
},
{
"instruction": "JMP 0",
"table": 3,
"measured": 3
},
{
"instruction": "IJMP",
"table": 2,
"measured": 2
},
{
"instruction": "RCALL .+0",
"table": 3,
"measured": 3
},
{
"instruction": "CALL 0",
"table": 4,
"measured": 4
},
{
"instruction": "ICALL",
"table": 3,
"measured": 3
},
{
"instruction": "RET",
"table": 4,
"measured": 4
},
{
"instruction": "RETI",
"table": 4,
"measured": 4
},
{
"instruction": "BRNE .+0 (taken)",
"table": 2,
"measured": 2
},
{
"instruction": "BRNE .+0 (not taken)",
"table": 1,
"measured": 1
},
{
"instruction": "BREQ .+0 (taken)",
"table": 2,
"measured": 2
},
{
"instruction": "BREQ .+0 (not taken)",
"table": 1,
"measured": 1
},
{
"instruction": "CPSE r16, r17 (no skip)",
"table": 1,
"measured": 1
},
{
"instruction": "CPSE r16, r17 (skips one word)",
"table": 2,
"measured": 2
},
{
"instruction": "CPSE r16, r17 (skips two words)",
"table": 3,
"measured": 3
},
{
"instruction": "SBRC r16, 0 (no skip)",
"table": 1,
"measured": 1
},
{
"instruction": "SBRC r16, 0 (skips one word)",
"table": 2,
"measured": 2
},
{
"instruction": "SBRS r16, 0 (skips two words)",
"table": 3,
"measured": 3
},
{
"instruction": "SBIS 0x05, 5 (no skip)",
"table": 1,
"measured": 1
},
{
"instruction": "SBIS 0x05, 5 (skips one word)",
"table": 2,
"measured": 2
},
{
"instruction": "SBIC 0x05, 5 (skips two words)",
"table": 3,
"measured": 3
},
{
"instruction": "SBI 0x05, 5",
"table": 2,
"measured": 2
},
{
"instruction": "CBI 0x05, 5",
"table": 2,
"measured": 2
},
{
"instruction": "IN r16, 0x05",
"table": 1,
"measured": 1
},
{
"instruction": "OUT 0x05, r16",
"table": 1,
"measured": 1
},
{
"instruction": "LDS r16, 0x0100",
"table": 2,
"measured": 2
},
{
"instruction": "STS 0x0100, r16",
"table": 2,
"measured": 2
},
{
"instruction": "LD r16, X",
"table": 2,
"measured": 2
},
{
"instruction": "LD r16, X+",
"table": 2,
"measured": 2
},
{
"instruction": "LD r16, -X",
"table": 2,
"measured": 2
},
{
"instruction": "LDD r16, Y+1",
"table": 2,
"measured": 2
},
{
"instruction": "LD r16, Z",
"table": 2,
"measured": 2
},
{
"instruction": "ST X, r16",
"table": 2,
"measured": 2
},
{
"instruction": "ST X+, r16",
"table": 2,
"measured": 2
},
{
"instruction": "ST -X, r16",
"table": 2,
"measured": 2
},
{
"instruction": "STD Y+1, r16",
"table": 2,
"measured": 2
},
{
"instruction": "PUSH r16",
"table": 2,
"measured": 2
},
{
"instruction": "POP r16",
"table": 2,
"measured": 2
},
{
"instruction": "LPM",
"table": 3,
"measured": 3
},
{
"instruction": "LPM r16, Z",
"table": 3,
"measured": 3
},
{
"instruction": "LPM r16, Z+",
"table": 3,
"measured": 3
},
{
"instruction": "SEI",
"table": 1,
"measured": 1
},
{
"instruction": "CLI",
"table": 1,
"measured": 1
},
{
"instruction": "BST r16, 0",
"table": 1,
"measured": 1
},
{
"instruction": "BLD r16, 0",
"table": 1,
"measured": 1
}
]
},
{
"engine": "rp2040js",
"version": "1.4.1-flowrs",
"source": "Raspberry Pi, RP2040 Datasheet, 2.4.3.3 Table 81 (Arm Cortex-M0+ instruction summary, zero wait states) and 2.3.1 (IOPORT accesses take one cycle)",
"not_covered": [
"PUSH with LR and POP with PC: measured, and one cycle short of the table each (note c counts LR and PC in N)",
"instruction fetch: rp2040js fetches code at no cost, so code run from flash takes no XIP cache miss or QSPI time",
"bus contention between the two cores, DMA and the debugger on the AHB-Lite crossbar",
"APB peripheral register accesses, which rp2040js charges 3 extra cycles to read and 4 to write; the datasheet gives no figure to check them against",
"WFI, WFE, SVC and BKPT, whose time is spent waiting or depends on the debug configuration"
],
"samples": [
{
"instruction": "MOVS r0, #1",
"table": 1,
"measured": 1
},
{
"instruction": "MOVS r1, r0",
"table": 1,
"measured": 1
},
{
"instruction": "MOV r8, r0",
"table": 1,
"measured": 1
},
{
"instruction": "MOV PC, r0",
"table": 2,
"measured": 2
},
{
"instruction": "ADDS r0, r0, #1",
"table": 1,
"measured": 1
},
{
"instruction": "ADDS r0, r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "ADD r0, r8",
"table": 1,
"measured": 1
},
{
"instruction": "ADD PC, r0",
"table": 2,
"measured": 2
},
{
"instruction": "ADDS r0, #1",
"table": 1,
"measured": 1
},
{
"instruction": "ADCS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "ADD SP, #4",
"table": 1,
"measured": 1
},
{
"instruction": "ADD r0, SP, #4",
"table": 1,
"measured": 1
},
{
"instruction": "ADR r0, .+4",
"table": 1,
"measured": 1
},
{
"instruction": "SUBS r0, r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "SUBS r0, #1",
"table": 1,
"measured": 1
},
{
"instruction": "SBCS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "SUB SP, #4",
"table": 1,
"measured": 1
},
{
"instruction": "RSBS r0, r1, #0",
"table": 1,
"measured": 1
},
{
"instruction": "MULS r0, r1, r0",
"table": 1,
"measured": 1
},
{
"instruction": "CMP r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "CMN r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "CMP r0, #1",
"table": 1,
"measured": 1
},
{
"instruction": "ANDS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "EORS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "ORRS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "BICS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "MVNS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "TST r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "LSLS r0, r1, #1",
"table": 1,
"measured": 1
},
{
"instruction": "LSLS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "LSRS r0, r1, #1",
"table": 1,
"measured": 1
},
{
"instruction": "LSRS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "ASRS r0, r1, #1",
"table": 1,
"measured": 1
},
{
"instruction": "ASRS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "RORS r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "LDR r0, [r1, #0] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDRH r0, [r1, #0] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDRB r0, [r1, #0] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDR r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDRH r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDRSH r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDRB r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDRSB r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "LDR r0, [PC, #0]",
"table": 2,
"measured": 2
},
{
"instruction": "LDR r0, [SP, #0]",
"table": 2,
"measured": 2
},
{
"instruction": "LDR r0, [r1, #0] (single-cycle I/O port)",
"table": 1,
"measured": 1
},
{
"instruction": "LDM r1!, {r0, r2}",
"table": 3,
"measured": 3
},
{
"instruction": "LDM r1, {r0, r1}",
"table": 3,
"measured": 3
},
{
"instruction": "STR r0, [r1, #0] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "STRH r0, [r1, #0] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "STRB r0, [r1, #0] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "STR r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "STRH r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "STRB r0, [r1, r2] (SRAM)",
"table": 2,
"measured": 2
},
{
"instruction": "STR r0, [SP, #0]",
"table": 2,
"measured": 2
},
{
"instruction": "STR r0, [r1, #0] (single-cycle I/O port)",
"table": 1,
"measured": 1
},
{
"instruction": "STM r1!, {r0, r2}",
"table": 3,
"measured": 3
},
{
"instruction": "PUSH {r0, r1}",
"table": 3,
"measured": 3
},
{
"instruction": "PUSH {r0, LR}",
"table": 3,
"measured": 2
},
{
"instruction": "POP {r0, r1}",
"table": 3,
"measured": 3
},
{
"instruction": "POP {r0, PC}",
"table": 5,
"measured": 4
},
{
"instruction": "B<cc> (taken)",
"table": 2,
"measured": 2
},
{
"instruction": "B<cc> (not taken)",
"table": 1,
"measured": 1
},
{
"instruction": "B .+2",
"table": 2,
"measured": 2
},
{
"instruction": "BL .+4",
"table": 3,
"measured": 3
},
{
"instruction": "BX r0",
"table": 2,
"measured": 2
},
{
"instruction": "BLX r0",
"table": 2,
"measured": 2
},
{
"instruction": "SXTH r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "SXTB r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "UXTH r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "UXTB r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "REV r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "REV16 r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "REVSH r0, r1",
"table": 1,
"measured": 1
},
{
"instruction": "CPSID i",
"table": 1,
"measured": 1
},
{
"instruction": "CPSIE i",
"table": 1,
"measured": 1
},
{
"instruction": "MRS r0, PRIMASK",
"table": 3,
"measured": 3
},
{
"instruction": "MSR PRIMASK, r0",
"table": 3,
"measured": 3
},
{
"instruction": "SEV",
"table": 1,
"measured": 1
},
{
"instruction": "YIELD",
"table": 1,
"measured": 1
},
{
"instruction": "NOP",
"table": 1,
"measured": 1
},
{
"instruction": "ISB",
"table": 3,
"measured": 3
},
{
"instruction": "DMB",
"table": 3,
"measured": 3
},
{
"instruction": "DSB",
"table": 3,
"measured": 3
}
]
}
]
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