### wai-quantum 0.5.1: neural-processor, matrix-extension, vector-unit, signal-processor and dataflow members

Additive. The default features, `full`, and every pinned digest are unchanged.

- **The neural-processor member** (`quantum_fabric_npu`, opt-in, macOS only). A neural
  processor computes in fp16 and does not document how it accumulates, so the member
  never relies on it: each 32-bit operand is split into eight 4-bit limbs, and the
  processor computes the fifteen coefficients `Σ_{i+j=s} a_i·b_j` of each product. Every
  limb product is at most 225 in size and every coefficient at most 1800, so every value
  it forms is an integer fp16 holds exactly, in any order. The host assembles each
  product exactly and applies `lanes::apply_words`'s arithmetic.
- **Credited by placement.** The member writes its model (one multiply, one sum) as the
  platform runtime's model description, compiles it at run time, and reads the
  runtime's compute plan: every operation must be placed on the neural processor, or
  the member is refused with the placement reported, so no CPU result is credited to the
  processor. It is then probed and certified against the pinned corpus digests, and
  the two model mutants (the multiply made an add, the sum a maximum) are caught.
- **The same program, portable.** `npu::onnx_limb_model` writes it in the portable model
  format (ONNX, opset 17: one `Mul`, one `ReduceSum`), with fp16 or int32 tensors, and
  `npu::expand_i32` lays out the int32 inputs; `examples/npu_onnx.rs` writes both models,
  a batch of inputs and the exact products they must give, so a neural processor
  reached through a runtime that reads that format can be checked against them.
- **Fixed** before release: `npu::f16_of(±2048)` subtracted past zero in a debug build.
- **The matrix-extension member** (`quantum_fabric_sme`, opt-in, aarch64 only): the
  gate's fixed-point arithmetic in the processor's streaming vector mode (SME), 64-bit
  lanes, by inline assembly; the host gathers each gate's pairs and checks each row's
  range. Its instructions exist only in that mode, so a kernel that ran, ran there.
  Detection reads the processor's feature flags (on Linux, `AT_HWCAP2`, which a
  user-mode emulator supplies for its guest); a runner under an emulator declares it,
  and every certificate carries that provenance. Three kernel mutants are compiled in.
- **The DSP vector-unit member** (`quantum_fabric_dsp`, opt-in, in a build for the signal
  processor with its 128-byte vector extension). The gate's arithmetic in 32-bit lanes,
  each 64-bit value a pair of words: the product is the vector unit's exact 32×32
  multiply (the 32-bit operand times the other's low half, unsigned, plus its high
  half, signed, sixteen bits up); the rounding constant's carry and each row's carries
  and borrows go into the high word; the shift is arithmetic over all 64 bits. The
  fabric gains the class `dsp`. Three kernel mutants are compiled in.
- **The CPU vector-unit members** (`quantum_fabric_vector`, opt-in): the gate's arithmetic
  in the processor's own vector extension — `avx2` on x86-64 (the 64-bit arithmetic
  shift, which the unit lacks, built from a logical shift and the sign bit), `sve` on
  aarch64 and `rvv` on riscv64, both written once for every vector length (the length
  set per pass and read back from the unit into the member's id). Silicon for `avx2`;
  `sve` at 128, 512 and 2048 bits and `rvv` at 128 and 1024 bits under the user-mode
  emulator. Three kernel mutants per instruction set.
- **The dataflow member** (`quantum_fabric_dataflow`, opt-in, Linux): the gate's arithmetic on
  the first RISC-V core of each of 32 compute tiles of a dataflow accelerator, each over a
  contiguous slice of a gate's pairs, two device generations (PCI 1e52:b140 and 1e52:401e),
  driven through the device's own library at the level of configuration space, memory
  windows, reset registers and clocks. The program comes from a new RV32IM
  encoder (`quantum_fabric::rv32`), whose listings an independent assembler turns into
  the same words; every 64-bit value is a pair of words. The library is the device's
  open-source simulator, built from source, and every certificate is labelled simulator.
- **The signal processor as a processor.** The bit-identity digests, the frame fixtures and
  the byte-pinning library tests pass for the processor's Linux target under its
  user-mode emulator. Emulator releases before 11.0 test a whole predicate register
  where the processor tests its low bit, in a branch on a predicate written in the same
  packet; compiled code relies on the low bit, and one library test fails under such an
  emulator. `ci/dsp/predicate_branch.c` shows which emulator does which, and the
  suites run on 11.1.1, built from its release.
- **CI.** `wai-quantum-npu.yml`: the device tests on the macOS runner's neural processor,
  and the same build on Linux, where the member is absent and says so.
  `wai-quantum-sme.yml`: the matrix-extension member's device tests for aarch64 Linux
  under the host's user-mode emulator, certificates labelled emulator; and the macOS
  runner, whose processor has no SME, finding no member. `wai-quantum-dsp.yml`: the
  signal processor's suites and the vector-unit member's device tests under the pinned
  emulator, after the emulator's own branch probe, and the same build on x86_64, where
  the member is absent and says so. `wai-quantum-vector.yml`: `avx2` on the container
  runner's processor, `sve` and `rvv` under the host's emulator at the lengths above (each
  leg checks the length the member read), and the macOS runner finding no member.

