processor-to-logic latency, AXI link: one board, the engine at its measured clock timer: CNTVCT_EL0 at 99.999 MHz, one tick 10.0 ns the timer alone (two reads, an ISB each) median 10 ns p10 10 p90 20 p99 20 max 18810 mean 12 (n 20000) EMIO signature read (a processor GPIO register) median 230 ns p10 230 p90 240 p99 240 max 28140 mean 236 (n 100000) AXI-Lite read, a link register median 230 ns p10 230 p90 230 p99 230 max 22360 mean 233 (n 100000) AXI-Lite read, an engine register median 240 ns p10 240 p90 240 p99 240 max 21600 mean 242 (n 100000) AXI-Lite write, a link register median 10 ns p10 10 p90 20 p99 20 max 10370 mean 14 (n 100000) AXI-Lite write, an engine register median 10 ns p10 10 p90 20 p99 20 max 38470 mean 14 (n 100000) AXI-Lite write then read (select a cell, read its field) median 460 ns p10 460 p90 580 p99 600 max 47820 mean 481 (n 100000) guarded read, as every job access goes (signature, then read) median 470 ns p10 460 p90 470 p99 470 max 19920 mean 469 (n 100000) a 1-entry write list by DMA, kick to done (4 writes, polls) median 7460 ns p10 7340 p90 7790 p99 9400 max 28330 mean 7645 (n 5000) a 512-entry write list by DMA (one page), kick to done median 20020 ns p10 19740 p90 20260 p99 29510 max 53911 mean 20197 (n 2000) = 39.1 ns an entry, 25.6 M register writes/s AXI, DMA and sequencer: a full table (64 levels x 128 fields, 32835 register writes): median 3.82 ms of 6, 116 ns a write AXI, DMA and sequencer: 65536 chains of 8 cells x 4 sweeps: 0.436 s, 6.65 us a chain, 150472 chains/s AXI, plain register accesses: a full table (64 levels x 128 fields, 32835 register writes): median 17.48 ms of 6, 532 ns a write AXI, plain register accesses: 16384 chains of 8 cells x 4 sweeps: 0.154 s, 9.43 us a chain, 106053 chains/s AXI accesses 1387388, DMA lists 8862, sequencer batches 257