The builds measured on 2026-11-06, and the testbenches' results. Copied from the tool's reports and
logs (its utilisation and timing reports, its build log, sha256sum), the lines that bear on the
README, without the reports' headers.

TOOL
  Vivado v2026.1 (lin64), build 6511674. Blocks: zynq_ultra_ps_e 3.5; in the AXI builds also
  axi_dwidth_converter 2.1 (twice) and axi_protocol_converter 2.1.
  The AXI builds ran with JOBS 1, general.maxThreads 2, under a 10 GB memory cap; the tool's own
  peak, as its log reports it, was 5,140 MB. An earlier attempt with JOBS 2 and no cap, on a 15 GB
  machine shared with other builds, ran the machine out of memory.

BUILDS (part xck26-sfvc784-2LV-c, 100 MHz)
  build                         sha256 of the .bit.bin                                             LUTs            registers  BRAM tiles  URAM  DSP  WNS      WHS
  AXI, final (write-back)       bb82505526e33403073924373a64d3519394344e9bf6d0193634c157e42b6dfb   28145 (24.03%)  13773      4           4     20   0.993 ns  0.012 ns
  AXI, first (no write-back)    3d84dbd355c9552c7593d3d5aa823284a4941acd25e5f3b7c92d5c0bc36ee441   27666 (23.62%)  13220      4           4     20   0.698 ns  0.012 ns
  EMIO, one engine              feea5015b2f8d85049fd48bcc66493a411d551326365f67b1db2ae65ec00074c   25539 (21.81%)  11121      0           4     20   0.294 ns  0.069 ns
  EMIO, four engines            2a73f02b5a6097bd251962b7d91f5ca368180db162941465aa32129130b06b09   80927 (69.10%)  44355      0           16    80   0.441 ns  0.010 ns
  (four engines: 13,925 of 14,640 slices, 95.12%; not loaded on the board this day)
  All four: 0 failing endpoints, setup and hold. The AXI builds report one critical warning, a
  false-path constraint for the EMIO port's synchroniser that finds no cell in them.

TESTBENCHES, on the scripts gen-tb records from this commit's model (sha256 of each script)
  EMIO  landscape_tb.script      4fb49e25f794849db750d688755ef452f05fb9146fd0cb016ad0b533dee5205e
        Icarus Verilog 13.0:  TB DONE: 174345 lines, 2668 checked reads, 0 mismatches, sim time 26571197000
        xsim v2026.1:         TB DONE: 174345 lines, 2668 checked reads, 0 mismatches, sim time 26571197000
  AXI   landscape_axi_tb.script  927b463dd40b9a3535fe77a770656415b58ce2dae33a93bf3299b3ab5252fc5c
        171 write lists, 50 batches, 50 write-backs
        Icarus Verilog 13.0:  TB DONE: 175830 lines, 4464 checked reads, 0 mismatches, sim time 6878426000
        xsim v2026.1:         TB DONE: 175830 lines, 4464 checked reads, 0 mismatches, sim time 6878426000
  A flipped expected word in a write-back's results (xsim, the earlier script):
        MISMATCH line 1231: written back chain 0 word 2 got 00000000 want f0000000
  The RTL the scripts ran against is the final AXI build's: no file under rtl/ that it is built
  from has changed since that build but for comments.