processor-to-logic latency, EMIO link: one board, the engine at its measured clock
  timer: CNTVCT_EL0 at 99.999 MHz, one tick 10.0 ns
  the timer alone (two reads, an ISB each)                   median      10 ns  p10      10  p90      20  p99      20  max    12120  mean      12  (n 20000)
  EMIO register read (handshake over GPIO)                   median     930 ns  p10     920  p90     930  p99     940  max   104301  mean     954  (n 5000)
  EMIO register write (handshake over GPIO)                  median     790 ns  p10     780  p90     800  p99     800  max    30540  mean     808  (n 5000)
  EMIO, plain register accesses: a full table (64 levels x 128 fields, 32835 register writes): median 29.00 ms of 6, 883 ns a write
  EMIO, plain register accesses: 4096 chains of 8 cells x 4 sweeps: 0.060 s, 14.61 us a chain, 68443 chains/s