// SPDX-License-Identifier: Apache-2.0
// K copies of the engine behind one EMIO port: address bits [15:13] pick the core, [12:0] are the
// core's own map. busy is ORed and done ANDed across cores. The host addresses one core at a time
// (CorePort) or all at once (BroadcastPort).
`timescale 1ns/1ps
`default_nettype none
module landscape_multi #(parameter integer K = 4) (
    input  wire        clk,
    input  wire [94:0] emio_o,
    output wire [94:0] emio_i
);
    (* ASYNC_REG = "TRUE" *) reg req_s1 = 1'b0, req_s2 = 1'b0;
    reg req_d = 1'b0;
    reg [6:0] por = 7'd0;
    wire por_done = por[6];
    always @(posedge clk) begin
        req_s1 <= emio_o[80];
        req_s2 <= req_s1;
        req_d  <= req_s2;
        if (!por_done) por <= por + 7'd1;
    end
    reg        stb = 1'b0, we = 1'b0, ack = 1'b0;
    reg [15:0] addr = 16'd0;
    reg [31:0] wdata = 32'd0;
    reg [3:0]  wait_cnt = 4'd0;
    always @(posedge clk) begin
        stb <= 1'b0;
        if (por_done && (req_s2 ^ req_d)) begin
            addr <= emio_o[79:64]; we <= emio_o[81]; wdata <= emio_o[31:0];
            stb <= 1'b1; wait_cnt <= 4'd4;
        end else if (wait_cnt != 4'd0) begin
            wait_cnt <= wait_cnt - 4'd1;
            if (wait_cnt == 4'd1) ack <= ~ack;
        end
    end
    wire [31:0] rd [0:K-1];
    wire [K-1:0] busy, done;
    genvar c;
    generate
        for (c = 0; c < K; c = c + 1) begin : CORE
            landscape_core core (
                .clk(clk), .reg_stb(stb & (addr[15:13] == c)), .reg_we(we),
                .reg_addr({3'b000, addr[12:0]}), .reg_wdata(wdata),
                .reg_rdata(rd[c]), .busy_o(busy[c]), .done_o(done[c])
            );
        end
    endgenerate
    reg [31:0] rdata = 32'd0;
    always @(posedge clk) rdata <= rd[addr[15:13] % K];
    assign emio_i = {10'd0, &done, |busy, ack, 18'd0, rdata, 32'd0};
endmodule
`default_nettype wire