// SPDX-License-Identifier: Apache-2.0
// KV260 top for the AXI link: the processing system gives the clock, an AXI-Lite master (its
// full-power-domain master port, through a width and a protocol converter), a high-performance slave port
// into DDR (through a width converter), and the EMIO lines. See landscape.tcl for why the widths
// are what they are. The reset is the fabric's own: a counter that holds the link's control in
// reset for 128 clocks after configuration, so the design does not depend on the state the
// processor's PL reset line was left in.
`timescale 1ns/1ps
module design_top();
    wire        pl_clk0;
    reg  [7:0]  por = 8'd0;
    always @(posedge pl_clk0) if (!por[7]) por <= por + 8'd1;
    wire        rstn = por[7];
    wire [39:0] l_awaddr, l_araddr;
    wire [31:0] l_wdata, l_rdata;
    wire        l_awvalid, l_awready, l_wvalid, l_wready, l_bvalid, l_bready, l_arvalid, l_arready, l_rvalid, l_rready;
    wire [1:0]  l_bresp, l_rresp;
    wire [3:0]  l_wstrb;
    wire [2:0]  l_awprot, l_arprot;
    wire [48:0] d_araddr;
    wire [7:0]  d_arlen;
    wire [2:0]  d_arsize, d_arprot;
    wire [1:0]  d_arburst, d_rresp;
    wire [3:0]  d_arcache;
    wire        d_arvalid, d_arready, d_rlast, d_rvalid, d_rready;
    wire [48:0] d_awaddr;
    wire [7:0]  d_awlen, d_wstrb;
    wire [2:0]  d_awsize, d_awprot;
    wire [1:0]  d_awburst, d_bresp;
    wire [3:0]  d_awcache;
    wire [63:0] d_wdata;
    wire        d_awvalid, d_awready, d_wlast, d_wvalid, d_wready, d_bvalid, d_bready;
    wire [63:0] d_rdata;
    wire [94:0] emio_o, emio_i;
    sys_wrapper ps_i (
        .pl_clk0(pl_clk0), .aresetn(rstn), .emio_o(emio_o), .emio_i(emio_i),
        .LITE_awaddr(l_awaddr), .LITE_awprot(l_awprot), .LITE_awvalid(l_awvalid), .LITE_awready(l_awready),
        .LITE_wdata(l_wdata), .LITE_wstrb(l_wstrb), .LITE_wvalid(l_wvalid), .LITE_wready(l_wready),
        .LITE_bresp(l_bresp), .LITE_bvalid(l_bvalid), .LITE_bready(l_bready),
        .LITE_araddr(l_araddr), .LITE_arprot(l_arprot), .LITE_arvalid(l_arvalid), .LITE_arready(l_arready),
        .LITE_rdata(l_rdata), .LITE_rresp(l_rresp), .LITE_rvalid(l_rvalid), .LITE_rready(l_rready),
        .DMA_araddr(d_araddr), .DMA_arlen(d_arlen), .DMA_arsize(d_arsize), .DMA_arburst(d_arburst),
        .DMA_arcache(d_arcache), .DMA_arprot(d_arprot), .DMA_arvalid(d_arvalid), .DMA_arready(d_arready),
        .DMA_arlock(1'b0), .DMA_arqos(4'd0), .DMA_arregion(4'd0),
        .DMA_rdata(d_rdata), .DMA_rresp(d_rresp), .DMA_rlast(d_rlast), .DMA_rvalid(d_rvalid), .DMA_rready(d_rready),
        .DMA_awaddr(d_awaddr), .DMA_awlen(d_awlen), .DMA_awsize(d_awsize), .DMA_awburst(d_awburst), .DMA_awcache(d_awcache),
        .DMA_awprot(d_awprot), .DMA_awvalid(d_awvalid), .DMA_awready(d_awready), .DMA_awlock(1'b0), .DMA_awqos(4'd0), .DMA_awregion(4'd0),
        .DMA_wdata(d_wdata), .DMA_wstrb(d_wstrb), .DMA_wlast(d_wlast), .DMA_wvalid(d_wvalid), .DMA_wready(d_wready),
        .DMA_bresp(d_bresp), .DMA_bvalid(d_bvalid), .DMA_bready(d_bready)
    );
    landscape_axi u (
        .clk(pl_clk0), .rstn(rstn),
        .s_awaddr(l_awaddr[31:0]), .s_awvalid(l_awvalid), .s_awready(l_awready), .s_wdata(l_wdata), .s_wvalid(l_wvalid),
        .s_wready(l_wready), .s_bresp(l_bresp), .s_bvalid(l_bvalid), .s_bready(l_bready),
        .s_araddr(l_araddr[31:0]), .s_arvalid(l_arvalid), .s_arready(l_arready), .s_rdata(l_rdata), .s_rresp(l_rresp),
        .s_rvalid(l_rvalid), .s_rready(l_rready),
        .m_araddr(d_araddr), .m_arlen(d_arlen), .m_arsize(d_arsize), .m_arburst(d_arburst), .m_arcache(d_arcache),
        .m_arprot(d_arprot), .m_arvalid(d_arvalid), .m_arready(d_arready), .m_rdata(d_rdata), .m_rresp(d_rresp),
        .m_rlast(d_rlast), .m_rvalid(d_rvalid), .m_rready(d_rready),
        .m_awaddr(d_awaddr), .m_awlen(d_awlen), .m_awsize(d_awsize), .m_awburst(d_awburst), .m_awcache(d_awcache),
        .m_awprot(d_awprot), .m_awvalid(d_awvalid), .m_awready(d_awready), .m_wdata(d_wdata), .m_wstrb(d_wstrb),
        .m_wlast(d_wlast), .m_wvalid(d_wvalid), .m_wready(d_wready), .m_bresp(d_bresp), .m_bvalid(d_bvalid), .m_bready(d_bready),
        .emio_i(emio_i)
    );
endmodule