37dfe98d2d
59 programs, each with what the reader must do with it: the language specification's 21 example programs, unchanged (those that run held to their results, the rest to the code that names the first construct the reader cannot hold exactly, or the example's own error), and a program for each construct with a reference written without it. stdgates.qasm applies every standard gate once, and its reference writes each in U and CX alone. Expectations: refused (a code), warns (every warning's code), deterministic (every shot's outcome), distribution (exact outcome probabilities), expectations (exact Pauli values), equivalent (a reference's unitary up to a global phase), exact (the bit-exact circuit takes it or refuses it with a code), outputs, timing and calibrations. bundle.json holds the cases with their text inline for builds that read no files; a test holds it equal to the files. CI: wai-quantum-lang.yml runs the reader's tests, the corpus natively, the reader built without the lowerings, and the corpus under wasm32-wasip2 by wasmtime; wai-web's wasm32 tests read every case through the page's engine (the wasm32 count goes from 8 to 9). Co-Authored-By: Claude Opus 5.5 <[email protected]>
77 lines
2.6 KiB
Text
77 lines
2.6 KiB
Text
OPENQASM 3.1;
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// The same gates, each written in U and CX alone.
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gate d_x a { U(pi, 0, pi) a; }
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gate d_y a { U(pi, pi / 2, pi / 2) a; }
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gate d_z a { U(0, 0, pi) a; }
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gate d_h a { U(pi / 2, 0, pi) a; }
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gate d_s a { U(0, 0, pi / 2) a; }
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gate d_sdg a { U(0, 0, -pi / 2) a; }
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gate d_t a { U(0, 0, pi / 4) a; }
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gate d_tdg a { U(0, 0, -pi / 4) a; }
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gate d_p(l) a { U(0, 0, l) a; }
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gate d_rx(t) a { U(t, -pi / 2, pi / 2) a; }
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gate d_ry(t) a { U(t, 0, 0) a; }
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gate d_rz(t) a { U(0, 0, t) a; }
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gate d_sx a { d_h a; d_s a; d_h a; }
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gate d_sxdg a { d_h a; d_sdg a; d_h a; }
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gate d_cz a, b { d_h b; CX a, b; d_h b; }
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gate d_cy a, b { d_sdg b; CX a, b; d_s b; }
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gate d_ch a, b { d_h b; d_sdg b; CX a, b; d_h b; d_t b; CX a, b; d_t b; d_h b; d_s b; d_x b; d_s a; }
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gate d_cp(l) a, b { d_p(l / 2) a; CX a, b; d_p(-l / 2) b; CX a, b; d_p(l / 2) b; }
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gate d_crz(l) a, b { d_rz(l / 2) b; CX a, b; d_rz(-l / 2) b; CX a, b; }
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gate d_crx(l) a, b { d_p(pi / 2) b; CX a, b; U(-l / 2, 0, 0) b; CX a, b; U(l / 2, -pi / 2, 0) b; }
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gate d_cry(l) a, b { d_ry(l / 2) b; CX a, b; d_ry(-l / 2) b; CX a, b; }
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gate d_cu(t, f, l, g) a, b { d_p(g) a; d_p((l + f) / 2) a; d_p((l - f) / 2) b; CX a, b; U(-t / 2, 0, -(f + l) / 2) b; CX a, b; U(t / 2, f, 0) b; }
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gate d_swap a, b { CX a, b; CX b, a; CX a, b; }
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gate d_iswap a, b { d_s a; d_s b; d_h a; CX a, b; CX b, a; d_h b; }
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gate d_rzz(t) a, b { CX a, b; d_rz(t) b; CX a, b; }
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gate d_rxx(t) a, b { d_h a; d_h b; d_rzz(t) a, b; d_h a; d_h b; }
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gate d_ryy(t) a, b { d_rx(pi / 2) a; d_rx(pi / 2) b; d_rzz(t) a, b; d_rx(-pi / 2) a; d_rx(-pi / 2) b; }
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gate d_ccx a, b, c { d_h c; CX b, c; d_tdg c; CX a, c; d_t c; CX b, c; d_tdg c; CX a, c; d_t b; d_t c; d_h c; CX a, b; d_t a; d_tdg b; CX a, b; }
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gate d_ccz a, b, c { d_h c; d_ccx a, b, c; d_h c; }
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gate d_cswap a, b, c { CX c, b; d_ccx a, b, c; CX c, b; }
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qubit[3] q;
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U(0.31, 0.72, -0.4) q[0];
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U(1.13, -0.25, 0.9) q[1];
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U(2.07, 0.5, 0.33) q[2];
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CX q[0], q[1];
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CX q[1], q[2];
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U(0.6, 1.1, -0.7) q[0];
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d_x q[0];
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d_y q[1];
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d_z q[2];
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d_h q[0];
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d_s q[1];
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d_sdg q[2];
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d_t q[0];
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d_tdg q[1];
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d_sx q[2];
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d_sxdg q[0];
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d_rx(0.41) q[1];
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d_ry(-1.3) q[2];
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d_rz(0.77) q[0];
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d_p(1.9) q[1];
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d_p(0.2) q[2];
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d_p(-0.6) q[0];
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U(pi / 2, 0.3, -1.2) q[1];
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U(0.8, 0.1, 2.2) q[2];
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U(1.4, -0.9, 0.35) q[0];
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CX q[0], q[1];
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CX q[2], q[0];
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d_cy q[1], q[2];
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d_cz q[2], q[0];
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d_ch q[0], q[2];
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d_cp(0.9) q[1], q[0];
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d_cp(-1.1) q[2], q[1];
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d_crx(0.6) q[0], q[1];
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d_cry(-0.8) q[1], q[2];
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d_crz(1.7) q[2], q[0];
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d_cu(0.5, 0.25, -0.75, 0.4) q[0], q[2];
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d_swap q[1], q[2];
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d_iswap q[0], q[1];
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d_rxx(0.45) q[1], q[2];
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d_ryy(-0.65) q[0], q[2];
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d_rzz(1.25) q[0], q[1];
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d_ccx q[0], q[1], q[2];
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d_ccz q[2], q[0], q[1];
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d_cswap q[1], q[2], q[0];
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