The model file is inert. The runtime and its compute target are the
phenomenon. This crate is how the runtime KNOWS its compute — the
corrective to a CPU-only substrate in a family that built fabric
everywhere on purpose.
DETECT — live probes only: CPU/NEON (32 cores, bit-exact reference
oracle), AMX via a real cblas_sgemm probe, Metal GPU via MPS device
query (M3 Ultra).
REACH — what ambient credentials open, nothing contacted: CUDA fleets
(Nebius, Lambda, Thunder, AWS, GCP, Azure, OVH, Scaleway, Linode),
Groq LPU, Cerebras WSE, SambaNova RDU, Tenstorrent via Koyeb.
Reachable never serves without a live executor handshake.
PLACE — cheapest-sufficient applied to silicon: projected uJ per op
from per-member costs (Measured/Benchmarked/Estimated provenance,
never self-upgraded) + per-class dispatch floors + the measured m>=8
matrix-block crossover. Recurrences stay on CPU; batched matmuls go
to the matrix block.
HONESTY GATES (tested): Uncertified members cannot serve — the Metal
GPU is detected but refuses work until parity-certified against the
CPU oracle (next wave, then the BF16 forwards ask the fabric instead
of hard-coding NEON). Efficiency by abstention is DOA.
Live on this box (examples/discover):
local/cpu-neon Detected BitExact serving
local/amx Detected Tolerance(128ulp) serving
local/metal-gpu Detected Uncertified gated
Also: backend-apple gains free-function sgemm_f32 and
mps_device_name/mps_matmul_fp32 re-exports. 11 tests. Costs are v0
projections; IOReport calibration lands with the loader integration.
Co-Authored-By: Claude Fable 5 <[email protected]>
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