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`discover_rocm` was `// TODO` returning nothing, behind `rocm = []` -- a feature with no dependency and no code, which compiled perfectly while providing nothing. The hardware is here (framework-128gb-0000: Radeon 8060S, gfx1151) so the backend can be real. HIP is opened at runtime with libloading rather than linked, which is the shape jouleclaw-loader-gguf already uses for CUDA and libnuma: nothing is needed at build time, so `--features rocm` compiles on a Mac or an NVIDIA host and finds no AMD devices there. Linking it would make the feature unbuildable wherever ROCm is absent, which is exactly how `cuda` came to demand a toolkit on every builder. Capabilities are read, not guessed. `hipGetDevicePropertiesR0600` gives warpSize, multiProcessorCount, sharedMemPerBlock, maxThreadsPerBlock and compute capability; the R0600 suffix is what pins that ABI, and the offsets come from the compiler on a ROCm 6.4 host -- `cc -D__HIP_PLATFORM_AMD__` plus `offsetof` -- not from counting padding by hand. The buffer is 4096 bytes against a 1472-byte struct so a later HIP that grew it still writes inside. Every value is range-checked before use: a wavefront is 32 or 64 and nothing else, CUs are 1..=1024, compute capability 1..=99. If a future layout moves a field this refuses with what it read, because the alternative is reporting garbage as hardware capability -- and `Capabilities` cannot say "unknown", so a zero there would read as "no compute units", "cannot do f16", and a `recommended_block_size()` of 0. Better to fail loudly than to be believed. f16/bf16/f8/int8 and the matrix tile are derived from the architecture, the way the CUDA path derives its own from compute capability. Bandwidth is an estimate per architecture, with gfx1151 called out: an APU shares LPDDR with the host and is nowhere near a discrete card. `examples/devices.rs` prints what discovery finds, so any host's fabric can be inspected directly. Co-Authored-By: Claude Opus 5 <[email protected]> |
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