c1137390e2
The crate is wai-quantum-landscape-fpga, beside the fabric's simulated FPGA member, which has its own workflow. The README gives the board and part as data, what the design does and refuses, what it takes to build, the build and load steps, the checks and the power protocol. No bitstream is distributed: the vendor tool's licence limits a bitstream holding its components to that vendor's devices, which Apache-2.0 does not carry, so the README gives the build and the sha256 of the bitstream measured. measurements/2026-11-05 holds the first version's raw power logs and the predictions committed before them, unchanged. The workflow runs the unit tests and every check against the model of the logic on each change. Co-Authored-By: Claude Opus 5.5 <[email protected]>
23 lines
1.5 KiB
Text
23 lines
1.5 KiB
Text
PRE-REGISTERED, 2026-11-05, written while the single-core campaign was still running on the board
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and before any of its numbers had been read, and before the four-core bitstream was ever loaded.
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WHY. The single-core prediction put gibbs-recall at ~5 mW, at or below the paired protocol's
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floor. The notes' own lesson (FEASIBILITY_parity_2026-10-04.txt): amplify the effect, don't average
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the noise. rtl/edge_multi.v puts four engines behind one port; `vqpu-edge meter <class> ... --cores 4`
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runs the same job on all four at once (BroadcastPort), so the effect is ~4x while the sensor quantum
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and drift stay put.
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WHAT IS MEASURED. The same run/halt protocol as the single-core campaign, on the four-core
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bitstream, 100 MHz, classes t0-recall and gibbs-recall.
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PREDICTIONS
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1. Scaling: P_dyn(4 cores) / P_dyn(1 core, this day's campaign) = 4.0, PASS range 3.4 .. 4.6 for
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t0-recall. Outside it, cores do not add independently (shared clock tree, placement density,
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rail), and the per-core numbers from the four-core build must not be divided by four.
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2. t0-recall, four cores: 4 x 122 = 488 mW (range 240 .. 1000), i.e. four times the single-core
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prediction, whatever the single-core measurement turns out to be.
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3. gibbs-recall, four cores: 4 x 5 = 20 mW (range 0 .. 80). If the single-core run could not
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resolve it, this is the number that can: at 20 mW and SE ~6 mW it is ~3 sigma.
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LABEL. Board-level, this KV260, this (four-core) design. Per-core figures from it are the four-core
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value divided by four only if prediction 1 passes.
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