c1137390e2
The crate is wai-quantum-landscape-fpga, beside the fabric's simulated FPGA member, which has its own workflow. The README gives the board and part as data, what the design does and refuses, what it takes to build, the build and load steps, the checks and the power protocol. No bitstream is distributed: the vendor tool's licence limits a bitstream holding its components to that vendor's devices, which Apache-2.0 does not carry, so the README gives the build and the sha256 of the bitstream measured. measurements/2026-11-05 holds the first version's raw power logs and the predictions committed before them, unchanged. The workflow runs the unit tests and every check against the model of the logic on each change. Co-Authored-By: Claude Opus 5.5 <[email protected]>
610 lines
11 KiB
Text
610 lines
11 KiB
Text
# class t0-recall
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# vqpu-edge meter passes=1 settle=0s samples=300 null=false sensor=/sys/class/hwmon/hwmon2/power1_input started=SystemTime { tv_sec: 1793906728, tv_nsec: 609413995 }
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# point pass=1 state=run jobs_per_s=12499749.7 updates_per_s=0.0 clock_hz=99997996
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# done SystemTime { tv_sec: 1793907328, tv_nsec: 966768242 }
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# passes used 1 of 1 (dropped: [])
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# run - halt = 140.0 +/- NaN mW (per-pass sd NaN); 1/1 passes positive; 6 sample excursions beyond 6 MAD
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# per-pass differences (mW): 140.0
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# board power while running 3260 mW; jobs/s 12499749.7; updates/s 0.0; measured PL clock 99.998 MHz
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