c2db9d17d1
The processor's master and high-performance ports boot at 128 bits and loading a bitstream does not change them, so the AXI build meets them with width converters and writes no processor register; ps-ports reads them, and the host touches no AXI address if they differ. The registers move to M_AXI_HPM0_FPD at 0xA000_0000, a port designs on this board have already used. A write master sends a batch's results to DDR, a page at a time, and the testbench checks every word it writes. Writes are now timed to their response. The class campaign's logs are added. Co-Authored-By: Claude Opus 5.5 <[email protected]>
610 lines
11 KiB
Text
610 lines
11 KiB
Text
# class t0-recall cores 1
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# wai-quantum-fpga meter passes=1 settle=0s samples=300 null=false sensor=/sys/class/hwmon/hwmon2/power1_input started=SystemTime { tv_sec: 1793968736, tv_nsec: 357321553 }
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# point pass=1 state=run jobs_per_s=12499751.7 updates_per_s=0.0 clock_hz=99998011
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# point pass=1 state=halt jobs_per_s=0.0 updates_per_s=0.0 clock_hz=99998009
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# done SystemTime { tv_sec: 1793969336, tv_nsec: 762934283 }
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# passes used 1 of 1 (dropped: [])
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# run - halt = 160.0 +/- NaN mW (per-pass sd NaN); 1/1 passes positive; 7 sample excursions beyond 6 MAD
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# per-pass differences (mW): 160.0
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# board power while running 3300 mW; jobs/s 12499751.7; updates/s 0.0; measured PL clock 99.998 MHz
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