c2db9d17d1
The processor's master and high-performance ports boot at 128 bits and loading a bitstream does not change them, so the AXI build meets them with width converters and writes no processor register; ps-ports reads them, and the host touches no AXI address if they differ. The registers move to M_AXI_HPM0_FPD at 0xA000_0000, a port designs on this board have already used. A write master sends a batch's results to DDR, a page at a time, and the testbench checks every word it writes. Writes are now timed to their response. The class campaign's logs are added. Co-Authored-By: Claude Opus 5.5 <[email protected]>
381 lines
7.6 KiB
Text
381 lines
7.6 KiB
Text
# class t0-recall cores 1
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# wai-quantum-fpga meter passes=6 settle=60s samples=30 null=false sensor=/sys/class/hwmon/hwmon2/power1_input started=SystemTime { tv_sec: 1793975822, tv_nsec: 342834432 }
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# pass state sample power_uW
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1 run 1 3190000
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1 run 2 3190000
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1 run 3 3610000
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1 run 4 3190000
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1 run 5 3200000
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1 run 6 3190000
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1 run 7 3190000
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1 run 8 3190000
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1 run 9 3190000
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1 run 10 3190000
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1 run 11 3180000
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1 run 12 3180000
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1 run 13 3200000
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1 run 14 3200000
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1 run 15 3180000
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1 run 16 3180000
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1 run 17 3180000
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1 run 18 3190000
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1 run 19 3180000
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1 run 20 3190000
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1 run 21 3190000
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1 run 22 3210000
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1 run 23 3180000
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1 run 24 3180000
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1 run 25 3190000
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1 run 26 3190000
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1 run 27 3190000
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1 run 28 3200000
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1 run 29 3190000
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1 run 30 3180000
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# point pass=1 state=run jobs_per_s=6249874.2 updates_per_s=0.0 clock_hz=49998982
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1 halt 1 3110000
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1 halt 2 3130000
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1 halt 3 3120000
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1 halt 4 3110000
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1 halt 5 3120000
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1 halt 6 3120000
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1 halt 7 3110000
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1 halt 8 3120000
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1 halt 9 3120000
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1 halt 10 3130000
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1 halt 11 3120000
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1 halt 12 3120000
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1 halt 13 3110000
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1 halt 14 3110000
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1 halt 15 3110000
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1 halt 16 3110000
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1 halt 17 3100000
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1 halt 18 3120000
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1 halt 19 3110000
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1 halt 20 3110000
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1 halt 21 3110000
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1 halt 22 3110000
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1 halt 23 3100000
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1 halt 24 3110000
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1 halt 25 3120000
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1 halt 26 3110000
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1 halt 27 3110000
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1 halt 28 3110000
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1 halt 29 3110000
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1 halt 30 3100000
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# point pass=1 state=halt jobs_per_s=0.0 updates_per_s=0.0 clock_hz=49998982
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2 halt 1 3110000
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2 halt 2 3110000
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2 halt 3 3110000
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2 halt 4 3110000
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2 halt 5 3110000
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2 halt 6 3110000
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2 halt 7 3130000
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2 halt 8 3110000
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2 halt 9 3110000
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2 halt 10 3100000
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2 halt 11 3110000
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2 halt 12 3110000
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2 halt 13 3110000
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2 halt 14 3110000
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2 halt 15 3110000
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2 halt 16 3110000
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2 halt 17 3100000
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2 halt 18 3110000
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2 halt 19 3110000
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2 halt 20 3100000
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2 halt 21 3120000
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2 halt 22 3130000
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2 halt 23 3110000
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2 halt 24 3100000
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2 halt 25 3110000
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2 halt 26 3120000
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2 halt 27 3100000
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2 halt 28 3120000
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2 halt 29 3120000
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2 halt 30 3140000
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# point pass=2 state=halt jobs_per_s=0.0 updates_per_s=0.0 clock_hz=49998981
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2 run 1 3190000
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2 run 2 3190000
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2 run 3 3180000
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2 run 4 3200000
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2 run 5 3190000
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2 run 6 3180000
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2 run 7 3190000
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2 run 8 3190000
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2 run 9 3180000
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2 run 10 3180000
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2 run 11 3190000
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2 run 12 3190000
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2 run 13 3190000
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2 run 14 3180000
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2 run 15 3190000
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2 run 16 3190000
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2 run 17 3200000
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2 run 18 3190000
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2 run 19 3210000
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2 run 20 3190000
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2 run 21 3200000
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2 run 22 3190000
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2 run 23 3200000
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2 run 24 3200000
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2 run 25 3190000
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2 run 26 3190000
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2 run 27 3200000
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2 run 28 3200000
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2 run 29 3190000
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2 run 30 3190000
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# point pass=2 state=run jobs_per_s=6249874.0 updates_per_s=0.0 clock_hz=49998981
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3 halt 1 3110000
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3 halt 2 3110000
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3 halt 3 3110000
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3 halt 4 3100000
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3 halt 5 3110000
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3 halt 6 3110000
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3 halt 7 3120000
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3 halt 8 3110000
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3 halt 9 3120000
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3 halt 10 3110000
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3 halt 11 3110000
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3 halt 12 3110000
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3 halt 13 3120000
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3 halt 14 3120000
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3 halt 15 3130000
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3 halt 16 3130000
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3 halt 17 3110000
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3 halt 18 3120000
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3 halt 19 3110000
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3 halt 20 3120000
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3 halt 21 3120000
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3 halt 22 3110000
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3 halt 23 3110000
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3 halt 24 3130000
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3 halt 25 3110000
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3 halt 26 3120000
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3 halt 27 3100000
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3 halt 28 3110000
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3 halt 29 3110000
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3 halt 30 3110000
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# point pass=3 state=halt jobs_per_s=0.0 updates_per_s=0.0 clock_hz=49998981
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3 run 1 3170000
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3 run 2 3170000
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3 run 3 3190000
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3 run 4 3200000
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3 run 5 3170000
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3 run 6 3170000
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3 run 7 3180000
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3 run 8 3170000
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3 run 9 3180000
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3 run 10 3170000
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3 run 11 3180000
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3 run 12 3190000
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3 run 13 3200000
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3 run 14 3170000
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3 run 15 3180000
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3 run 16 3180000
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3 run 17 3180000
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3 run 18 3180000
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3 run 19 3180000
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3 run 20 3180000
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3 run 21 3200000
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3 run 22 3190000
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3 run 23 3200000
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3 run 24 3190000
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3 run 25 3190000
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3 run 26 3190000
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3 run 27 3190000
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3 run 28 3200000
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3 run 29 3190000
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3 run 30 3190000
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# point pass=3 state=run jobs_per_s=6249873.9 updates_per_s=0.0 clock_hz=49998980
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4 halt 1 3120000
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4 halt 2 3100000
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4 halt 3 3100000
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4 halt 4 3100000
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4 halt 5 3100000
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4 halt 6 3100000
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4 halt 7 3110000
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4 halt 8 3100000
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4 halt 9 3110000
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4 halt 10 3100000
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4 halt 11 3100000
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4 halt 12 3100000
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4 halt 13 3100000
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4 halt 14 3100000
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4 halt 15 3100000
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4 halt 16 3100000
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4 halt 17 3110000
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4 halt 18 3100000
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4 halt 19 3100000
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4 halt 20 3100000
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4 halt 21 3090000
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4 halt 22 3110000
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4 halt 23 3110000
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4 halt 24 3100000
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4 halt 25 3100000
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4 halt 26 3100000
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4 halt 27 3100000
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4 halt 28 3090000
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4 halt 29 3100000
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4 halt 30 3100000
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# point pass=4 state=halt jobs_per_s=0.0 updates_per_s=0.0 clock_hz=49998980
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4 run 1 3180000
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4 run 2 3190000
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4 run 3 3180000
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4 run 4 3190000
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4 run 5 3190000
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4 run 6 3200000
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4 run 7 3190000
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4 run 8 3190000
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4 run 9 3170000
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4 run 10 3190000
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4 run 11 3190000
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4 run 12 3190000
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4 run 13 3190000
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4 run 14 3190000
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4 run 15 3180000
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4 run 16 3190000
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4 run 17 3200000
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4 run 18 3190000
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4 run 19 3190000
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4 run 20 3200000
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4 run 21 3200000
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4 run 22 3190000
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4 run 23 3180000
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4 run 24 3180000
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4 run 25 3170000
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4 run 26 3180000
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4 run 27 3170000
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4 run 28 3180000
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4 run 29 3200000
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4 run 30 3210000
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# point pass=4 state=run jobs_per_s=6249873.9 updates_per_s=0.0 clock_hz=49998979
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5 halt 1 3100000
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5 halt 2 3100000
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5 halt 3 3110000
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5 halt 4 3110000
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5 halt 5 3100000
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5 halt 6 3110000
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5 halt 7 3100000
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5 halt 8 3100000
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5 halt 9 3100000
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5 halt 10 3110000
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5 halt 11 3110000
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5 halt 12 3110000
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5 halt 13 3110000
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5 halt 14 3100000
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5 halt 15 3100000
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5 halt 16 3100000
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5 halt 17 3100000
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5 halt 18 3120000
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5 halt 19 3100000
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5 halt 20 3090000
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5 halt 21 3100000
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5 halt 22 3090000
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5 halt 23 3100000
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5 halt 24 3100000
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5 halt 25 3100000
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5 halt 26 3110000
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5 halt 27 3100000
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5 halt 28 3100000
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5 halt 29 3110000
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5 halt 30 3100000
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# point pass=5 state=halt jobs_per_s=0.0 updates_per_s=0.0 clock_hz=49998980
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5 run 1 3180000
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5 run 2 3180000
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5 run 3 3200000
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5 run 4 3190000
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5 run 5 3180000
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5 run 6 3190000
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5 run 7 3190000
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5 run 8 3180000
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5 run 9 3190000
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5 run 10 3190000
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5 run 11 3170000
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5 run 12 3190000
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5 run 13 3180000
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5 run 14 3190000
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5 run 15 3180000
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5 run 16 3180000
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5 run 17 3220000
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5 run 18 3190000
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5 run 19 3180000
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5 run 20 3190000
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5 run 21 3180000
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5 run 22 3180000
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5 run 23 3180000
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5 run 24 3180000
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5 run 25 3180000
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5 run 26 3180000
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5 run 27 3200000
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5 run 28 3180000
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5 run 29 3190000
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5 run 30 3190000
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# point pass=5 state=run jobs_per_s=6249878.2 updates_per_s=0.0 clock_hz=49999014
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6 halt 1 3120000
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6 halt 2 3100000
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6 halt 3 3100000
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6 halt 4 3100000
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6 halt 5 3110000
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6 halt 6 3110000
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6 halt 7 3100000
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6 halt 8 3110000
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6 halt 9 3100000
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6 halt 10 3110000
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6 halt 11 3100000
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6 halt 12 3110000
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6 halt 13 3100000
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6 halt 14 3110000
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6 halt 15 3110000
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6 halt 16 3100000
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6 halt 17 3100000
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6 halt 18 3100000
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6 halt 19 3110000
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6 halt 20 3100000
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6 halt 21 3110000
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6 halt 22 3110000
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6 halt 23 3120000
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6 halt 24 3120000
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6 halt 25 3110000
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6 halt 26 3110000
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6 halt 27 3100000
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6 halt 28 3110000
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6 halt 29 3100000
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6 halt 30 3100000
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# point pass=6 state=halt jobs_per_s=0.0 updates_per_s=0.0 clock_hz=49999283
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6 run 1 3190000
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6 run 2 3180000
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6 run 3 3190000
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6 run 4 3190000
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6 run 5 3170000
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6 run 6 3190000
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6 run 7 3200000
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6 run 8 3180000
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6 run 9 3200000
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6 run 10 3190000
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6 run 11 3350000
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6 run 12 3190000
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6 run 13 3190000
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6 run 14 3190000
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6 run 15 3180000
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6 run 16 3550000
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6 run 17 3190000
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6 run 18 3190000
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6 run 19 3190000
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6 run 20 3180000
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6 run 21 3180000
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6 run 22 3210000
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6 run 23 3320000
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6 run 24 3190000
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6 run 25 3180000
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6 run 26 3180000
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6 run 27 3190000
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6 run 28 3190000
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6 run 29 3190000
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6 run 30 3210000
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# point pass=6 state=run jobs_per_s=6249906.7 updates_per_s=0.0 clock_hz=49999241
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# done SystemTime { tv_sec: 1793976903, tv_nsec: 28061803 }
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# passes used 6 of 6 (dropped: [])
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# run - halt = 80.0 +/- 2.6 mW (per-pass sd 6.3); 6/6 passes positive; 5 sample excursions beyond 6 MAD
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# per-pass differences (mW): 80.0 80.0 70.0 90.0 80.0 80.0
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# board power while running 3187 mW; jobs/s 6249880.1; updates/s 0.0; measured PL clock 49.999 MHz
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# pre-registered prediction 80.0 mW: measured/predicted = 1.00, 0.0 sigma from it
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