c2db9d17d1
The processor's master and high-performance ports boot at 128 bits and loading a bitstream does not change them, so the AXI build meets them with width converters and writes no processor register; ps-ports reads them, and the host touches no AXI address if they differ. The registers move to M_AXI_HPM0_FPD at 0xA000_0000, a port designs on this board have already used. A write master sends a batch's results to DDR, a page at a time, and the testbench checks every word it writes. Writes are now timed to their response. The class campaign's logs are added. Co-Authored-By: Claude Opus 5.5 <[email protected]>
483 lines
8.2 KiB
Text
483 lines
8.2 KiB
Text
# kv_runhalt bitstream=ev_rdet.bit.bin gpio=594 settle=60s passes=8 samples=30
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# done
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