c1137390e2
The crate is wai-quantum-landscape-fpga, beside the fabric's simulated FPGA member, which has its own workflow. The README gives the board and part as data, what the design does and refuses, what it takes to build, the build and load steps, the checks and the power protocol. No bitstream is distributed: the vendor tool's licence limits a bitstream holding its components to that vendor's devices, which Apache-2.0 does not carry, so the README gives the build and the sha256 of the bitstream measured. measurements/2026-11-05 holds the first version's raw power logs and the predictions committed before them, unchanged. The workflow runs the unit tests and every check against the model of the logic on each change. Co-Authored-By: Claude Opus 5.5 <[email protected]>
67 lines
2.6 KiB
Verilog
67 lines
2.6 KiB
Verilog
// SPDX-License-Identifier: Apache-2.0
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// The job port: register reads and writes carried over the PS's EMIO GPIO lines.
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//
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// Why not AXI. A PS load or store to an AXI address whose PL slave is gone never completes, and it
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// takes the whole board with it until someone power-cycles it. This board is shared and remote, and
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// another session's reload can replace the design between two accesses. An EMIO line is a PS
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// register: with the design gone a read returns junk, the ID check fails, and the job gets an
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// error. The cost is speed: about 1.6 us a register access, measured.
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//
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// The PS offers 95 EMIO lines (banks 3, 4 and 31 bits of 5):
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// emio_o[31:0] wdata (bank 3) emio_i[63:32] rdata (bank 4)
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// emio_o[79:64] addr (bank 5, 15:0) emio_o[80] req (toggle) emio_o[81] we
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// emio_i[82] ack (toggle) emio_i[83] busy emio_i[84] done
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// busy and done are wired straight through, so polling for the end of a job takes no transaction.
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//
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// Handshake: the host writes wdata, then addr/we/req in one register write. The req edge crosses a
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// two-flop synchroniser, so by the time it is seen addr, we and wdata have long been stable; they are
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// latched then, and ack toggles once the access is done.
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`timescale 1ns/1ps
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`default_nettype none
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module landscape_port (
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input wire clk,
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input wire [94:0] emio_o,
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output wire [94:0] emio_i
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);
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(* ASYNC_REG = "TRUE" *) reg req_s1 = 1'b0, req_s2 = 1'b0;
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reg req_d = 1'b0;
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reg [6:0] por = 7'd0; // the PS's lines may hold anything when we are configured
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wire por_done = por[6];
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always @(posedge clk) begin
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req_s1 <= emio_o[80];
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req_s2 <= req_s1;
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req_d <= req_s2;
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if (!por_done) por <= por + 7'd1;
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end
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reg stb = 1'b0, we = 1'b0, ack = 1'b0;
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reg [15:0] addr = 16'd0;
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reg [31:0] wdata = 32'd0;
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reg [3:0] wait_cnt = 4'd0;
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wire [31:0] rdata;
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wire busy, done;
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always @(posedge clk) begin
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stb <= 1'b0;
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if (por_done && (req_s2 ^ req_d)) begin
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addr <= emio_o[79:64];
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we <= emio_o[81];
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wdata <= emio_o[31:0];
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stb <= 1'b1;
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wait_cnt <= 4'd4;
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end else if (wait_cnt != 4'd0) begin
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wait_cnt <= wait_cnt - 4'd1;
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if (wait_cnt == 4'd1) ack <= ~ack;
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end
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end
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landscape_core core (
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.clk(clk), .reg_stb(stb), .reg_we(we), .reg_addr(addr), .reg_wdata(wdata),
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.reg_rdata(rdata), .busy_o(busy), .done_o(done)
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);
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assign emio_i = {10'd0, done, busy, ack, 18'd0, rdata, 32'd0};
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endmodule
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`default_nettype wire
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