c1137390e2
The crate is wai-quantum-landscape-fpga, beside the fabric's simulated FPGA member, which has its own workflow. The README gives the board and part as data, what the design does and refuses, what it takes to build, the build and load steps, the checks and the power protocol. No bitstream is distributed: the vendor tool's licence limits a bitstream holding its components to that vendor's devices, which Apache-2.0 does not carry, so the README gives the build and the sha256 of the bitstream measured. measurements/2026-11-05 holds the first version's raw power logs and the predictions committed before them, unchanged. The workflow runs the unit tests and every check against the model of the logic on each change. Co-Authored-By: Claude Opus 5.5 <[email protected]>
10 lines
397 B
Verilog
10 lines
397 B
Verilog
// SPDX-License-Identifier: Apache-2.0
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// KV260 top: the PS provides pl_clk0 and the EMIO lines; there is no other PL I/O.
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`timescale 1ns/1ps
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module design_top();
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wire pl_clk0;
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wire [94:0] emio_o;
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wire [94:0] emio_i;
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sys_wrapper ps_i (.pl_clk0(pl_clk0), .emio_o(emio_o), .emio_i(emio_i));
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landscape_port u (.clk(pl_clk0), .emio_o(emio_o), .emio_i(emio_i));
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endmodule
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