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The lock and reloads. load takes the board lock before it reconfigures, and the session check sees other runs of this tool and its scripts (their own parents excepted), so a reload waits for the job that holds the board. The scripts do not hold the lock across the steps they run. A reload of the same design, which passes the signature and the ID, is seen by the engine's uptime counter and its reset BOUND register: the engine checks both before it takes a workload or a table as loaded and after every job, and refuses a result read across a reload. A batch that comes back short, and a sampled chain whose sweep count is wrong, are refused. The AXI port. It checks the port's write width as well as its read width; it fills a result page with the illegal cell pair before a write-back and refuses a result still holding it; it refuses a transfer whose page moved. It is written against two traits, so a software link tests it off the board: the guard, the DMA, the sequencer's count, the write-back's layout, dropped accesses. Tests. lowered_settle's five cases and 300 random workloads with fields to 2^40 against the reference; the joint test counts against the chains requested and checks the control's cell family. CI gates on the change, requires tests to run, denies clippy warnings, certifies the model member, runs a job on it, builds on linux-arm64, and replays both testbenches in Icarus Verilog (scripts/run_tb.sh). The names check reads .v, .tcl, .xdc and .dat files. The build. The tool version and each block's version are enforced; the multi-core build refuses the AXI link. The documents. The latency table says how each row was timed; the engine's share of a chain is its own clock count; the sampling energy carries its error and its floor; the known answer is placed in time; the step response is reported; derived figures are marked; the scope of the meter, the guard's window and the DMA's locked pages are stated; provenance says what the private code declared; old names are gone; the build and simulator results have a raw record. Co-Authored-By: Claude Opus 5.5 <[email protected]>
26 lines
1.5 KiB
Shell
Executable file
26 lines
1.5 KiB
Shell
Executable file
#!/bin/sh
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# SPDX-License-Identifier: Apache-2.0
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# Build the engine's bitstream and convert it for the Linux FPGA manager. Needs the vendor's tool on
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# PATH, at the version this design was built and measured with: Vivado 2026.1 (landscape.tcl stops on
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# any other). Its no-charge licence tier covers this part. The design uses no licensed IP: its vendor
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# blocks are the processing system's configuration and, in the AXI build, the tool's AXI width and
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# protocol converters. Run from an empty directory:
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# sh /path/to/wai-quantum-landscape-fpga/scripts/build_bitstream.sh [MHz] [cores] [axi|emio]
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# The AXI link is the default; the multi-core build (cores above 1) has the EMIO link only.
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# JOBS (default 4) is how many tool runs go at once. On a small machine, run with JOBS=1 and a memory
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# cap: the tool peaked at 5.1 GB alone, and a machine with 15 GB shared with other work ran out.
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set -e
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FREQ=${1:-100}
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CORES=${2:-1}
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LINK=${3:-axi}
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if [ "$CORES" -gt 1 ]; then LINK=emio; fi
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HERE=$(cd "$(dirname "$0")/.." && pwd)
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vivado -version | head -1
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vivado -mode batch -nojournal -source "$HERE/landscape.tcl" -tclargs FREQ "$FREQ" TAG landscape JOBS "${JOBS:-4}" CORES "$CORES" LINK "$LINK" > build.log 2>&1
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grep -E "IMPL_STATUS|BITSTREAM" build.log
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BIT=$(ls ev_landscape/ev_landscape.runs/impl_1/*.bit)
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printf 'all:\n{\n %s\n}\n' "$BIT" > landscape.bif
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bootgen -image landscape.bif -arch zynqmp -process_bitstream bin -w on
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cp "$BIT.bin" landscape.bit.bin
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grep -A6 "Design Timing Summary" ev_landscape.timing.rpt | tail -1
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sha256sum landscape.bit.bin
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