d4867b1b83
The lock and reloads. load takes the board lock before it reconfigures, and the session check sees other runs of this tool and its scripts (their own parents excepted), so a reload waits for the job that holds the board. The scripts do not hold the lock across the steps they run. A reload of the same design, which passes the signature and the ID, is seen by the engine's uptime counter and its reset BOUND register: the engine checks both before it takes a workload or a table as loaded and after every job, and refuses a result read across a reload. A batch that comes back short, and a sampled chain whose sweep count is wrong, are refused. The AXI port. It checks the port's write width as well as its read width; it fills a result page with the illegal cell pair before a write-back and refuses a result still holding it; it refuses a transfer whose page moved. It is written against two traits, so a software link tests it off the board: the guard, the DMA, the sequencer's count, the write-back's layout, dropped accesses. Tests. lowered_settle's five cases and 300 random workloads with fields to 2^40 against the reference; the joint test counts against the chains requested and checks the control's cell family. CI gates on the change, requires tests to run, denies clippy warnings, certifies the model member, runs a job on it, builds on linux-arm64, and replays both testbenches in Icarus Verilog (scripts/run_tb.sh). The names check reads .v, .tcl, .xdc and .dat files. The build. The tool version and each block's version are enforced; the multi-core build refuses the AXI link. The documents. The latency table says how each row was timed; the engine's share of a chain is its own clock count; the sampling energy carries its error and its floor; the known answer is placed in time; the step response is reported; derived figures are marked; the scope of the meter, the guard's window and the DMA's locked pages are stated; provenance says what the private code declared; old names are gone; the build and simulator results have a raw record. Co-Authored-By: Claude Opus 5.5 <[email protected]>
81 lines
3 KiB
Verilog
81 lines
3 KiB
Verilog
// SPDX-License-Identifier: Apache-2.0
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// Replays a session recorded from the host's software model (`wai-quantum-landscape-fpga gen-tb landscape_tb.script`) against the RTL,
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// through the EMIO port and its synchroniser, with the PS side deliberately off the PL clock.
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// Every read must return what the model returned. A mismatch names the script line.
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`timescale 1ns/1ps
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module tb;
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reg clk = 0;
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always #5 clk = ~clk; // pl_clk0, 100 MHz
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reg [94:0] emio_o = 95'd0;
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wire [94:0] emio_i;
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`ifdef MULTI
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landscape_multi #(.K(4)) dut (.clk(clk), .emio_o(emio_o), .emio_i(emio_i));
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`else
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landscape_port dut (.clk(clk), .emio_o(emio_o), .emio_i(emio_i));
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`endif
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integer fd, r, errors, reads, line, t;
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reg [31:0] op, a, d, m, got;
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reg req;
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task txn(input we, input [15:0] addr, input [31:0] wdata, output [31:0] rdata);
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reg ack0;
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begin
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ack0 = emio_i[82];
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emio_o[31:0] = wdata;
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#37; // a PS bus write, some time before the next
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req = ~req;
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emio_o[81] = we;
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emio_o[79:64] = addr;
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emio_o[80] = req;
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t = 0;
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while (emio_i[82] == ack0) begin
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#13;
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t = t + 1;
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if (t > 20000) begin
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$display("TIMEOUT waiting for ack at script line %0d", line);
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$finish;
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end
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end
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rdata = emio_i[63:32];
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#29;
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end
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endtask
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initial begin
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errors = 0; reads = 0; line = 0; req = 0;
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#3000; // past the port's power-on hold-off
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fd = $fopen("landscape_tb.script", "r");
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if (fd == 0) begin $display("no script"); $finish; end
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r = $fscanf(fd, "%s", op);
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while (r == 1) begin
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line = line + 1;
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if (op == "W") begin
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r = $fscanf(fd, " %h %h", a, d);
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txn(1'b1, a[15:0], d, got);
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end else if (op == "R") begin
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r = $fscanf(fd, " %h %h %h", a, d, m);
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txn(1'b0, a[15:0], 32'd0, got);
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reads = reads + 1;
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if ((got & m) !== (d & m)) begin
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errors = errors + 1;
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if (errors <= 25) $display("MISMATCH line %0d: R %h got %h want %h", line, a[15:0], got, d);
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end
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end else if (op == "I") begin
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t = 0;
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while (emio_i[83]) begin
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#50;
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t = t + 1;
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if (t > 2000000) begin $display("TIMEOUT busy at line %0d", line); $finish; end
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end
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#20;
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end else begin
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$display("bad op at line %0d", line);
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$finish;
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end
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r = $fscanf(fd, "%s", op);
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end
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$display("TB DONE: %0d lines, %0d checked reads, %0d mismatches, sim time %0t", line, reads, errors, $time);
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$finish;
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end
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endmodule
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