c2db9d17d1
The processor's master and high-performance ports boot at 128 bits and loading a bitstream does not change them, so the AXI build meets them with width converters and writes no processor register; ps-ports reads them, and the host touches no AXI address if they differ. The registers move to M_AXI_HPM0_FPD at 0xA000_0000, a port designs on this board have already used. A write master sends a batch's results to DDR, a page at a time, and the testbench checks every word it writes. Writes are now timed to their response. The class campaign's logs are added. Co-Authored-By: Claude Opus 5.5 <[email protected]>
286 lines
13 KiB
Verilog
286 lines
13 KiB
Verilog
// SPDX-License-Identifier: Apache-2.0
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// Replays a session recorded from the host's software model in its AXI form (`gen-tb --axi`)
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// against the AXI link (rtl/landscape_axi.v) and the engine behind it: register accesses over
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// AXI-Lite, write lists through the DMA from a memory model that answers with irregular delays and
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// several bursts outstanding, and batches of chains through the sequencer, whose results are read
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// from the result RAM and written back to the memory model. Every read and every word written back
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// must be what the model returned. A mismatch names the line.
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`timescale 1ns/1ps
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module tb;
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reg clk = 0;
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always #5 clk = ~clk; // pl_clk0, 100 MHz
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reg rstn = 0;
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// AXI-Lite master
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reg [31:0] awaddr = 0, wdata = 0, araddr = 0;
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reg awvalid = 0, wvalid = 0, bready = 0, arvalid = 0, rready = 0;
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wire awready, wready, bvalid, arready, rvalid;
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wire [1:0] bresp, rresp;
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wire [31:0] rdata;
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// DMA read port
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wire [48:0] m_araddr;
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wire [7:0] m_arlen;
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wire [2:0] m_arsize, m_arprot;
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wire [1:0] m_arburst;
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wire [3:0] m_arcache;
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wire m_arvalid, m_rready;
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reg m_arready = 0, m_rvalid = 0, m_rlast = 0;
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reg [63:0] m_rdata = 0;
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reg [1:0] m_rresp = 0;
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// DMA write port
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wire [48:0] m_awaddr;
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wire [7:0] m_awlen, m_wstrb;
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wire [2:0] m_awsize, m_awprot;
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wire [1:0] m_awburst;
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wire [3:0] m_awcache;
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wire [63:0] m_wdata;
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wire m_awvalid, m_wlast, m_wvalid, m_bready;
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reg m_awready = 0, m_wready = 0, m_bvalid = 0;
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reg [1:0] m_bresp = 0;
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wire [94:0] emio_i;
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landscape_axi dut (
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.clk(clk), .rstn(rstn),
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.s_awaddr(awaddr), .s_awvalid(awvalid), .s_awready(awready), .s_wdata(wdata), .s_wvalid(wvalid),
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.s_wready(wready), .s_bresp(bresp), .s_bvalid(bvalid), .s_bready(bready),
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.s_araddr(araddr), .s_arvalid(arvalid), .s_arready(arready), .s_rdata(rdata), .s_rresp(rresp),
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.s_rvalid(rvalid), .s_rready(rready),
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.m_araddr(m_araddr), .m_arlen(m_arlen), .m_arsize(m_arsize), .m_arburst(m_arburst), .m_arcache(m_arcache),
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.m_arprot(m_arprot), .m_arvalid(m_arvalid), .m_arready(m_arready), .m_rdata(m_rdata), .m_rresp(m_rresp),
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.m_rlast(m_rlast), .m_rvalid(m_rvalid), .m_rready(m_rready),
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.m_awaddr(m_awaddr), .m_awlen(m_awlen), .m_awsize(m_awsize), .m_awburst(m_awburst), .m_awcache(m_awcache),
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.m_awprot(m_awprot), .m_awvalid(m_awvalid), .m_awready(m_awready), .m_wdata(m_wdata), .m_wstrb(m_wstrb),
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.m_wlast(m_wlast), .m_wvalid(m_wvalid), .m_wready(m_wready), .m_bresp(m_bresp), .m_bvalid(m_bvalid), .m_bready(m_bready),
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.emio_i(emio_i)
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);
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// ---- DDR: a memory model behind the high-performance port --------------------------------------
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localparam [48:0] BASE = 49'h0_1000_0000;
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reg [63:0] mem [0:65535];
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reg [48:0] q_addr [0:15];
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reg [7:0] q_len [0:15];
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reg [4:0] q_head = 0, q_tail = 0;
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reg [8:0] beat = 0;
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integer seed = 7;
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wire [4:0] q_used = q_tail - q_head;
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always @(posedge clk) begin
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// address channel: accept when there is room, sometimes late
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m_arready <= 1'b0;
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if (m_arvalid && !m_arready && q_used < 5'd8 && ($random(seed) & 3) != 0) begin
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m_arready <= 1'b1;
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q_addr[q_tail[3:0]] <= m_araddr;
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q_len[q_tail[3:0]] <= m_arlen;
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q_tail <= q_tail + 5'd1;
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if (m_arsize != 3'd3 || m_arburst != 2'b01) begin $display("DMA: bad size or burst"); $finish; end
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if ((m_araddr[11:0] + ({4'd0, m_arlen} + 12'd1) * 12'd8) > 13'h1000 && m_araddr[11:0] != 12'd0) begin
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$display("DMA: a burst crosses a 4 KiB page at %h", m_araddr); $finish;
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end
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end
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// data channel: one beat at a time, with gaps
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if (m_rvalid && m_rready) begin
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m_rvalid <= 1'b0;
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if (m_rlast) begin q_head <= q_head + 5'd1; beat <= 0; end
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else beat <= beat + 9'd1;
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end else if (!m_rvalid && q_used != 5'd0 && ($random(seed) % 5) != 0) begin
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m_rvalid <= 1'b1;
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m_rdata <= mem[(q_addr[q_head[3:0]] - BASE) / 8 + beat];
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m_rlast <= (beat == {1'b0, q_len[q_head[3:0]]});
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m_rresp <= 2'b00;
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end
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end
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// ---- the write side of the memory model: one burst at a time, with gaps ------------------------
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localparam [48:0] WB_BASE = 49'h0_2000_0000;
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reg [63:0] wmem [0:4095];
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reg [48:0] w_addr = 0;
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reg w_open = 0;
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always @(posedge clk) begin
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m_awready <= 1'b0;
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m_wready <= 1'b0;
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if (m_bvalid && m_bready) m_bvalid <= 1'b0;
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if (m_awvalid && !m_awready && !w_open && ($random(seed) & 1) != 0) begin
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m_awready <= 1'b1;
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w_addr <= m_awaddr;
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w_open <= 1'b1;
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if (m_awsize != 3'd3 || m_awburst != 2'b01) begin $display("write-back: bad size or burst"); $finish; end
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if ({1'b0, m_awaddr[11:0]} + ({5'd0, m_awlen} + 13'd1) * 13'd8 > 13'h1000) begin
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$display("write-back: a burst crosses a 4 KiB page at %h", m_awaddr); $finish;
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end
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end
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if (m_wvalid && !m_wready && w_open && ($random(seed) & 3) != 0) m_wready <= 1'b1;
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if (m_wvalid && m_wready) begin
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if (m_wstrb != 8'hFF) begin $display("write-back: bad strobes"); $finish; end
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wmem[(w_addr - WB_BASE) / 8] <= m_wdata;
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w_addr <= w_addr + 49'd8;
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if (m_wlast) begin w_open <= 1'b0; m_bvalid <= 1'b1; m_bresp <= 2'b00; end
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end
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end
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// ---- AXI-Lite master tasks --------------------------------------------------------------------
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// The master drives just after a clock edge and samples the slave's outputs at the edge, as
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// they were before it: a handshake completes on the edge where valid and ready were both high.
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integer line, t;
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reg a_ok, w_ok, done_hs;
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task axi_write(input [15:0] word, input [31:0] d);
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begin
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@(posedge clk); #1;
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awaddr = 32'hA000_0000 | ({16'd0, word} << 2); wdata = d; awvalid = 1; wvalid = 1;
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t = 0;
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while (awvalid || wvalid) begin
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@(posedge clk);
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a_ok = awready; w_ok = wready;
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#1;
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if (a_ok) awvalid = 0;
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if (w_ok) wvalid = 0;
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t = t + 1;
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if (t > 1000) begin $display("TIMEOUT write %h at line %0d", word, line); $finish; end
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end
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bready = 1;
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done_hs = 0; t = 0;
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while (!done_hs) begin
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@(posedge clk);
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done_hs = bvalid;
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#1;
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t = t + 1;
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if (t > 1000) begin $display("TIMEOUT b at line %0d", line); $finish; end
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end
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bready = 0;
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end
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endtask
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task axi_read(input [15:0] word, output [31:0] d);
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begin
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@(posedge clk); #1;
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araddr = 32'hA000_0000 | ({16'd0, word} << 2); arvalid = 1;
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t = 0;
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while (arvalid) begin
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@(posedge clk);
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a_ok = arready;
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#1;
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if (a_ok) arvalid = 0;
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t = t + 1;
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if (t > 1000) begin $display("TIMEOUT ar %h at line %0d", word, line); $finish; end
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end
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rready = 1;
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done_hs = 0; t = 0;
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while (!done_hs) begin
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@(posedge clk);
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done_hs = rvalid;
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d = rdata;
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#1;
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t = t + 1;
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if (t > 1000) begin $display("TIMEOUT r at line %0d", line); $finish; end
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end
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rready = 0;
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end
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endtask
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integer fd, r, errors, reads, k, n, i, polls, longest;
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reg [31:0] op, a, d, m, got, word;
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reg [63:0] ent_a, ent_d;
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initial begin
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errors = 0; reads = 0; line = 0; longest = 0;
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repeat (20) @(posedge clk);
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rstn = 1;
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repeat (5) @(posedge clk);
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if (emio_i[7:0] !== 8'hA5) begin $display("no signature"); $finish; end
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axi_read(16'h8000, got);
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if (got !== 32'h4C415849) begin $display("wrapper ID %h", got); $finish; end
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fd = $fopen("landscape_axi_tb.script", "r");
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if (fd == 0) begin $display("no script"); $finish; end
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r = $fscanf(fd, "%s", op);
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while (r == 1) begin
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line = line + 1;
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if (op == "W") begin
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r = $fscanf(fd, " %h %h", a, d);
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axi_write(a[15:0], d);
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end else if (op == "R") begin
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r = $fscanf(fd, " %h %h %h", a, d, m);
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axi_read(a[15:0], got);
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reads = reads + 1;
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if ((got & m) !== (d & m)) begin
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errors = errors + 1;
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if (errors <= 25) $display("MISMATCH line %0d: R %h got %h want %h", line, a[15:0], got, d);
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end
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end else if (op == "I") begin
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got = 1; polls = 0;
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while (got[0]) begin
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axi_read(16'h0002, got);
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polls = polls + 1;
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if (polls > 200000) begin $display("TIMEOUT busy at line %0d", line); $finish; end
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end
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end else if (op == "D") begin
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r = $fscanf(fd, " %d", n);
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for (k = 0; k < n; k = k + 1) begin
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r = $fscanf(fd, " %h %h", ent_a, ent_d);
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mem[k] = {16'd0, ent_a[15:0], ent_d[31:0]};
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line = line + 1;
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end
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axi_write(16'h8002, BASE[31:0]);
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axi_write(16'h8003, {15'd0, BASE[48:32]});
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axi_write(16'h8004, n);
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axi_write(16'h8005, 1);
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got = 2; polls = 0;
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while (got[1]) begin
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axi_read(16'h8001, got);
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polls = polls + 1;
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if (polls > 200000) begin $display("TIMEOUT DMA at line %0d", line); $finish; end
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end
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if (got[2]) begin $display("DMA error at line %0d", line); errors = errors + 1; end
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end else if (op == "Q") begin
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r = $fscanf(fd, " %d", n);
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axi_write(16'h8010, n);
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axi_write(16'h8011, 1);
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// an engine access while the sequencer holds the engine: answered at once, dropped
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axi_read(16'h0000, got);
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if (got !== 32'hDEADBEEF) begin $display("an engine read during a batch returned %h at line %0d", got, line); errors = errors + 1; end
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axi_read(16'h8008, got);
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if (got !== 32'd1) begin $display("DROPS %0d after one dropped read, line %0d", got, line); errors = errors + 1; end
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axi_write(16'h8008, 0);
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got = 1; polls = 0;
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while (got[0]) begin
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axi_read(16'h8001, got);
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polls = polls + 1;
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if (polls > 2000000) begin $display("TIMEOUT sequencer at line %0d", line); $finish; end
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end
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if (polls > longest) longest = polls;
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end else if (op == "K") begin
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// the results of the last batch, written back: n chains, six words each, to check
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r = $fscanf(fd, " %d", n);
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axi_read(16'h8025, d);
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axi_write(16'h8020, WB_BASE[31:0]);
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axi_write(16'h8021, {15'd0, WB_BASE[48:32]});
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axi_write(16'h8022, 0);
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axi_write(16'h8023, n);
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axi_write(16'h8024, 1);
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got = 8; polls = 0;
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while (got[3]) begin
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axi_read(16'h8001, got);
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polls = polls + 1;
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if (polls > 200000) begin $display("TIMEOUT write-back at line %0d", line); $finish; end
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end
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if (got[4]) begin $display("write-back error at line %0d", line); errors = errors + 1; end
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axi_read(16'h8025, got);
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if (got !== d + 1) begin $display("write-back did not run at line %0d", line); errors = errors + 1; end
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for (k = 0; k < n; k = k + 1) begin
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for (i = 0; i < 6; i = i + 1) begin
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r = $fscanf(fd, " %h", d);
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line = line + 1;
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word = (i % 2) ? wmem[k * 4 + i / 2][63:32] : wmem[k * 4 + i / 2][31:0];
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reads = reads + 1;
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if (word !== d) begin
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errors = errors + 1;
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if (errors <= 25) $display("MISMATCH line %0d: written back chain %0d word %0d got %h want %h", line, k, i, word, d);
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end
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end
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end
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end else begin
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$display("bad op at line %0d", line);
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$finish;
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end
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r = $fscanf(fd, "%s", op);
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end
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$display("TB DONE: %0d lines, %0d checked reads, %0d mismatches, sim time %0t", line, reads, errors, $time);
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$finish;
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end
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endmodule
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