49c9d04fbc
Built alone from an empty CARGO_HOME, its tests passed, and flowrsc checked, ran and exported a document from the conformance corpus; the export built alone. Co-Authored-By: Claude Opus 5.5 <[email protected]>
134 lines
4.4 KiB
ArmAsm
134 lines
4.4 KiB
ArmAsm
/*
|
|
* Reset, vectors and the interrupt entry of the bare-metal fixture (MIPS32r2, the M4K).
|
|
* The CPU starts at 0xBFC00000 with BEV and ERL set (PIC32 FRM Section 2); this sets up the
|
|
* stack, copies .data, clears .bss, places EBase at 0x9D000000, picks 32-byte vector spacing
|
|
* and vectored interrupts (IntCtl.VS, Cause.IV), and leaves BEV and ERL for main().
|
|
*/
|
|
.set noreorder
|
|
.set noat
|
|
.section .reset, "ax"
|
|
.globl _reset
|
|
_reset:
|
|
la $sp, _stack
|
|
la $t0, _data_load
|
|
la $t1, _data
|
|
la $t2, _edata
|
|
1: beq $t1, $t2, 2f
|
|
nop
|
|
lw $t3, 0($t0)
|
|
sw $t3, 0($t1)
|
|
addiu $t0, 4
|
|
b 1b
|
|
addiu $t1, 4
|
|
2: la $t1, _bss
|
|
la $t2, _ebss
|
|
3: beq $t1, $t2, 4f
|
|
nop
|
|
sw $zero, 0($t1)
|
|
b 3b
|
|
addiu $t1, 4
|
|
4: la $t0, 0x9D000000
|
|
mtc0 $t0, $15, 1 /* EBase */
|
|
li $t0, 0x20
|
|
mtc0 $t0, $12, 1 /* IntCtl.VS = 1: 32 bytes */
|
|
li $t0, 0x00800000
|
|
mtc0 $t0, $13 /* Cause.IV */
|
|
mtc0 $zero, $12 /* Status: BEV, ERL, EXL clear; IPL 0; IE off */
|
|
ehb
|
|
la $t0, main
|
|
jr $t0
|
|
nop
|
|
|
|
/* The configuration words: POSC (HS) through the PLL /2 x20 /1 = 80 MHz from 8 MHz, PBCLK /1,
|
|
* watchdog off, priority 7 on the shadow set (DEVCFG3 FSRSSEL 111). DEVCFG3 is lowest. */
|
|
.section .config, "a"
|
|
.word 0xffffffff /* DEVCFG3 */
|
|
.word 0xfff879d9 /* DEVCFG2: FPLLIDIV /2, FPLLMUL x20, FPLLODIV /1 */
|
|
.word 0xff74ce5b /* DEVCFG1: FNOSC POSC+PLL, POSCMOD HS, FPBDIV /1, FWDTEN 0 */
|
|
.word 0xffffffff /* DEVCFG0 */
|
|
|
|
.section .vectors, "ax"
|
|
.org 0x180 /* general exception */
|
|
la $k0, exc_handler
|
|
jr $k0
|
|
nop
|
|
.org 0x200 /* vector 0: core timer, at priority 7 on the shadow set */
|
|
la $k0, ct_isr
|
|
jr $k0
|
|
nop
|
|
.org 0x200 + 8 * 32 /* vector 8: Timer2, priority 3, normal registers */
|
|
la $k0, t2_isr
|
|
jr $k0
|
|
nop
|
|
.org 0x200 + 64 * 32
|
|
|
|
.text
|
|
/* On the shadow set: the interrupted code's registers are in the other set, so nothing is
|
|
* saved; the stack pointer comes over from the previous set (RDPGPR). */
|
|
ct_isr:
|
|
/* rdpgpr $sp, $sp: COP0 rs=01010, rt=29, rd=29 (LLVM's assembler does not take it for
|
|
* this CPU, so it is spelt out). */
|
|
.word 0x41400000 | (29 << 16) | (29 << 11)
|
|
la $k0, ct_seen_sp /* what RDPGPR read, for main() to check */
|
|
sw $sp, 0($k0)
|
|
addiu $sp, $sp, -16
|
|
la $t0, ct_handler
|
|
jalr $t0
|
|
nop
|
|
addiu $sp, $sp, 16
|
|
eret
|
|
nop
|
|
|
|
/* On the normal registers: save what the C handler may clobber. */
|
|
t2_isr:
|
|
addiu $sp, $sp, -96
|
|
sw $at, 4($sp)
|
|
sw $v0, 8($sp)
|
|
sw $v1, 12($sp)
|
|
sw $a0, 16($sp)
|
|
sw $a1, 20($sp)
|
|
sw $a2, 24($sp)
|
|
sw $a3, 28($sp)
|
|
sw $t0, 32($sp)
|
|
sw $t1, 36($sp)
|
|
sw $t2, 40($sp)
|
|
sw $t3, 44($sp)
|
|
sw $t4, 48($sp)
|
|
sw $t5, 52($sp)
|
|
sw $t6, 56($sp)
|
|
sw $t7, 60($sp)
|
|
sw $t8, 64($sp)
|
|
sw $t9, 68($sp)
|
|
sw $ra, 72($sp)
|
|
mfhi $k0
|
|
sw $k0, 76($sp)
|
|
mflo $k0
|
|
sw $k0, 80($sp)
|
|
la $t0, t2_handler
|
|
jalr $t0
|
|
nop
|
|
lw $k0, 80($sp)
|
|
mtlo $k0
|
|
lw $k0, 76($sp)
|
|
mthi $k0
|
|
lw $at, 4($sp)
|
|
lw $v0, 8($sp)
|
|
lw $v1, 12($sp)
|
|
lw $a0, 16($sp)
|
|
lw $a1, 20($sp)
|
|
lw $a2, 24($sp)
|
|
lw $a3, 28($sp)
|
|
lw $t0, 32($sp)
|
|
lw $t1, 36($sp)
|
|
lw $t2, 40($sp)
|
|
lw $t3, 44($sp)
|
|
lw $t4, 48($sp)
|
|
lw $t5, 52($sp)
|
|
lw $t6, 56($sp)
|
|
lw $t7, 60($sp)
|
|
lw $t8, 64($sp)
|
|
lw $t9, 68($sp)
|
|
lw $ra, 72($sp)
|
|
addiu $sp, $sp, 96
|
|
eret
|
|
nop
|