49c9d04fbc
Built alone from an empty CARGO_HOME, its tests passed, and flowrsc checked, ran and exported a document from the conformance corpus; the export built alone. Co-Authored-By: Claude Opus 5.5 <[email protected]>
154 lines
4.8 KiB
ArmAsm
154 lines
4.8 KiB
ArmAsm
/*
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* Reset, vectors and interrupt entries of the PIC32MZ bare-metal fixture (MIPS32r2: the
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* microAptiv UP of the MZ EC, the M-Class core of the MZ EF). The CPU starts at 0xBFC00000
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* with BEV and ERL set, in MIPS32 as DEVCFG0.BOOTISA says (FRM Section 50.23). This sets up the
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* stack, copies .data, clears .bss, places EBase at 0x9D000000 and leaves BEV and ERL for
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* main(). The controller presents each vector's offset from EBase that its OFFx register holds
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* (DS60001108H 8.5.2): main() writes OFF000 and OFF009 with the handlers below.
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*/
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.set noreorder
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.set noat
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.section .reset, "ax"
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.globl _reset
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_reset:
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la $sp, _stack
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la $t0, _data_load
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la $t1, _data
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la $t2, _edata
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1: beq $t1, $t2, 2f
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nop
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lw $t3, 0($t0)
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sw $t3, 0($t1)
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addiu $t0, 4
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b 1b
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addiu $t1, 4
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2: la $t1, _bss
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la $t2, _ebss
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3: beq $t1, $t2, 4f
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nop
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sw $zero, 0($t1)
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b 3b
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addiu $t1, 4
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4: la $t0, 0x9D000000
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mtc0 $t0, $15, 1 /* EBase */
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li $t0, 0x00800000
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mtc0 $t0, $13 /* Cause.IV */
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mtc0 $zero, $12 /* Status: BEV, ERL, EXL clear; IPL 0; IE off */
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ehb
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la $t0, main
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jr $t0
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nop
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/*
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* The configuration words: MICROCHIP_MZ_STARTER_KIT.hex's (chipKIT32/PIC32-avrdude-
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* bootloader) -- a 24 MHz clock (EC) /3 x50 /2 = 200 MHz from the system PLL, BOOTISA MIPS32,
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* the watchdog and the deadman timer off -- with DEVCFG3.IOL1WAY 1 (the erased value).
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* DEVCFG3 is lowest (DS60001320H Registers 34-3 to 34-6).
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*/
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.section .config, "a"
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.word 0xbeffffff /* DEVCFG3: IOL1WAY 1 */
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.word 0xfff9b11a /* DEVCFG2: FPLLIDIV /3, FPLLRNG 5-10, POSC, x50, /2 */
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.word 0x03743839 /* DEVCFG1: FNOSC SPLL, POSCMOD EC, FWDTEN 0, FDMTEN 0 */
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.word 0xfffff7f7 /* DEVCFG0: BOOTISA MIPS32 */
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.section .vectors, "ax"
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.org 0x180 /* general exception */
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la $k0, exc_handler
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jr $k0
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nop
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.org 0x200
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.text
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/* The core timer's: priority 7, on shadow set 1 (PRISS.PRI7SS); the stack pointer comes over
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* from the interrupted set (RDPGPR), nothing else needs saving. */
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.globl ct_isr
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ct_isr:
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.word 0x41400000 | (29 << 16) | (29 << 11) /* rdpgpr $sp, $sp */
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la $k0, ct_seen_sp
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sw $sp, 0($k0)
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addiu $sp, $sp, -16
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la $t0, ct_handler
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jalr $t0
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nop
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addiu $sp, $sp, 16
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eret
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nop
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/* Every other: on the normal registers, saving what the C handler may clobber. */
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.macro isr name, handler
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.globl \name
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\name:
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addiu $sp, $sp, -96
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sw $at, 4($sp)
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sw $v0, 8($sp)
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sw $v1, 12($sp)
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sw $a0, 16($sp)
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sw $a1, 20($sp)
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sw $a2, 24($sp)
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sw $a3, 28($sp)
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sw $t0, 32($sp)
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sw $t1, 36($sp)
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sw $t2, 40($sp)
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sw $t3, 44($sp)
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sw $t4, 48($sp)
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sw $t5, 52($sp)
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sw $t6, 56($sp)
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sw $t7, 60($sp)
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sw $t8, 64($sp)
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sw $t9, 68($sp)
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sw $ra, 72($sp)
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mfhi $k0
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sw $k0, 76($sp)
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mflo $k0
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sw $k0, 80($sp)
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la $t0, \handler
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jalr $t0
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nop
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lw $k0, 80($sp)
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mtlo $k0
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lw $k0, 76($sp)
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mthi $k0
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lw $at, 4($sp)
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lw $v0, 8($sp)
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lw $v1, 12($sp)
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lw $a0, 16($sp)
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lw $a1, 20($sp)
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lw $a2, 24($sp)
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lw $a3, 28($sp)
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lw $t0, 32($sp)
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lw $t1, 36($sp)
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lw $t2, 40($sp)
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lw $t3, 44($sp)
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lw $t4, 48($sp)
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lw $t5, 52($sp)
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lw $t6, 56($sp)
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lw $t7, 60($sp)
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lw $t8, 64($sp)
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lw $t9, 68($sp)
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lw $ra, 72($sp)
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addiu $sp, $sp, 96
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eret
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nop
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.endm
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isr t2_isr, t2_handler
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isr cn_isr, cn_handler
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/*
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* sqrt(2) on the FPU, as a 64-bit double in FR=1 mode (the MZ EF's FPU: DS60001320H 3.3;
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* the caller has set Status.CU1 and FR): returns its bits, high word in $v1.
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*/
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.globl fpu_sqrt2
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.set push
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.set hardfloat
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.set fp=64
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fpu_sqrt2:
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lui $t0, 0x4000 /* 2.0 = 0x40000000_00000000 */
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mtc1 $zero, $f2
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mthc1 $t0, $f2
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sqrt.d $f0, $f2
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mfc1 $v0, $f0
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mfhc1 $v1, $f0
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jr $ra
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nop
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.set pop
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