49c9d04fbc
Built alone from an empty CARGO_HOME, its tests passed, and flowrsc checked, ran and exported a document from the conformance corpus; the export built alone. Co-Authored-By: Claude Opus 5.5 <[email protected]>
140 lines
4.4 KiB
ArmAsm
140 lines
4.4 KiB
ArmAsm
/*
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* Reset, vectors and the interrupt entries of the PIC32MX1xx/2xx bare-metal fixture
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* (MIPS32r2, the M4K with no shadow register set: DS60001168L "7.0 Interrupt Controller",
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* one register set, so every handler saves what it clobbers). The CPU starts at 0xBFC00000
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* with BEV and ERL set (PIC32 FRM Section 2); this sets up the stack, copies .data, clears
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* .bss, places EBase at 0x9D000000, picks 32-byte vector spacing and vectored interrupts
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* (IntCtl.VS, Cause.IV), and leaves BEV and ERL for main().
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*/
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.set noreorder
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.set noat
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.section .reset, "ax"
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.globl _reset
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_reset:
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la $sp, _stack
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la $t0, _data_load
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la $t1, _data
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la $t2, _edata
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1: beq $t1, $t2, 2f
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nop
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lw $t3, 0($t0)
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sw $t3, 0($t1)
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addiu $t0, 4
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b 1b
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addiu $t1, 4
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2: la $t1, _bss
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la $t2, _ebss
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3: beq $t1, $t2, 4f
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nop
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sw $zero, 0($t1)
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b 3b
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addiu $t1, 4
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4: la $t0, 0x9D000000
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mtc0 $t0, $15, 1 /* EBase */
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li $t0, 0x20
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mtc0 $t0, $12, 1 /* IntCtl.VS = 1: 32 bytes */
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li $t0, 0x00800000
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mtc0 $t0, $13 /* Cause.IV */
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mtc0 $zero, $12 /* Status: BEV, ERL, EXL clear; IPL 0; IE off */
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ehb
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la $t0, main
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jr $t0
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nop
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/*
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* The configuration words (DS60001168L Registers 27-1..27-4): chipKIT_Pi.hex's -- an 8 MHz
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* crystal (HS) through the PLL /2 x20 /2 = 40 MHz, PBCLK /1, the watchdog off -- but DEVCFG3
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* erased, so IOL1WAY is 1: CFGCON.IOLOCK, once set, stays set. DEVCFG3 is lowest.
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*/
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.section .config, "a"
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.word 0xffffffff /* DEVCFG3: IOL1WAY 1 */
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.word 0xfff979d9 /* DEVCFG2: FPLLIDIV /2, FPLLMUL x20, FPLLODIV /2 */
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.word 0xff6a0e5b /* DEVCFG1: FNOSC POSC+PLL, POSCMOD HS, FPBDIV /1, FWDTEN 0 */
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.word 0x7ffffffb /* DEVCFG0 */
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/* Each vector saves the caller-saved registers and calls its C handler (no shadow set). */
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.macro isr name, handler
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\name:
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addiu $sp, $sp, -96
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sw $at, 4($sp)
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sw $v0, 8($sp)
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sw $v1, 12($sp)
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sw $a0, 16($sp)
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sw $a1, 20($sp)
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sw $a2, 24($sp)
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sw $a3, 28($sp)
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sw $t0, 32($sp)
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sw $t1, 36($sp)
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sw $t2, 40($sp)
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sw $t3, 44($sp)
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sw $t4, 48($sp)
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sw $t5, 52($sp)
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sw $t6, 56($sp)
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sw $t7, 60($sp)
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sw $t8, 64($sp)
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sw $t9, 68($sp)
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sw $ra, 72($sp)
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mfhi $k0
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sw $k0, 76($sp)
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mflo $k0
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sw $k0, 80($sp)
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la $t0, \handler
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jalr $t0
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nop
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lw $k0, 80($sp)
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mtlo $k0
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lw $k0, 76($sp)
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mthi $k0
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lw $at, 4($sp)
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lw $v0, 8($sp)
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lw $v1, 12($sp)
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lw $a0, 16($sp)
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lw $a1, 20($sp)
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lw $a2, 24($sp)
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lw $a3, 28($sp)
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lw $t0, 32($sp)
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lw $t1, 36($sp)
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lw $t2, 40($sp)
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lw $t3, 44($sp)
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lw $t4, 48($sp)
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lw $t5, 52($sp)
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lw $t6, 56($sp)
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lw $t7, 60($sp)
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lw $t8, 64($sp)
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lw $t9, 68($sp)
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lw $ra, 72($sp)
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addiu $sp, $sp, 96
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eret
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nop
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.endm
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.section .vectors, "ax"
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.org 0x180 /* general exception */
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la $k0, exc_handler
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jr $k0
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nop
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/* The MX1xx/2xx's vectors (DS60001168L Table 7-1): core timer 0, Timer2 8, INT4 19,
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* change notice 34. */
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.org 0x200 + 0 * 32
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la $k0, ct_isr
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jr $k0
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nop
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.org 0x200 + 8 * 32
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la $k0, t2_isr
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jr $k0
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nop
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.org 0x200 + 19 * 32
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la $k0, int4_isr
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jr $k0
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nop
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.org 0x200 + 34 * 32
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la $k0, cn_isr
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jr $k0
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nop
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.org 0x200 + 64 * 32
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.text
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isr ct_isr, ct_handler
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isr t2_isr, t2_handler
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isr int4_isr, int4_handler
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isr cn_isr, cn_handler
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