49c9d04fbc
Built alone from an empty CARGO_HOME, its tests passed, and flowrsc checked, ran and exported a document from the conformance corpus; the export built alone. Co-Authored-By: Claude Opus 5.5 <[email protected]>
26 lines
986 B
ArmAsm
26 lines
986 B
ArmAsm
/*
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* The PIC32 panel's instruction-count demo: RG6 toggled by a loop whose length is known, so the
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* pin's rate follows from the instruction count alone. Entered through -kernel with no reset
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* code of its own (the machine jumps to the entry, as after a chipKIT bootloader).
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*
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* Each half period is one store to LATGINV, 125 NOPs, the branch and its delay slot: 128
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* instructions. Under -icount shift=4 every instruction is 16 ns, so a period is 256 x 16 ns =
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* 4096 ns: 244140.625 Hz, duty exactly 50 % (both halves are the same instructions).
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.set noreorder
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.set noat
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.text
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.globl _start
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_start:
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li $t0, 0xBF886184 /* TRISGCLR */
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li $t1, 1 << 6
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sw $t1, 0($t0) /* RG6 an output */
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li $t0, 0xBF8861AC /* LATGINV */
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1: sw $t1, 0($t0)
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.rept 125
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nop
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.endr
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b 1b
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nop
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