wai-quantum 0.5.1: neural-processor, matrix-extension, vector-unit, signal-processor and dataflow members #263

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dcharlot merged 15 commits from wai/quantum-npu into main 2026-10-15 10:08:35 -04:00

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dcharlot commented 2026-10-15 01:12:08 -04:00

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wai-quantum 0.5.1: five more members of the fabric, each certified bit-exact against the CPU reference's pinned corpus digests, and the provenance of each certificate stated (silicon, emulator or simulator).

Members

Feature	Member	Class	Where it was certified
quantum_fabric_npu	the platform's neural processor: each 32-bit operand as eight 4-bit limbs, every limb product and sum an integer fp16 holds exactly, the host assembling. Credited only where the runtime's compute plan puts every operation on the neural processor; mutants go through the same check	npu	silicon (two machines)
quantum_fabric_sme	the processor's streaming vector mode, 64-bit lanes	cpu-matrix	silicon; emulator
quantum_fabric_vector	the processor's own vector extension: avx2, sve and rvv, the scalable kernels written once for every vector length, the length read back from the unit	cpu	avx2 silicon; sve at 128, 512 and 2048 bits and rvv at 128 and 1024 bits under the emulator
quantum_fabric_dsp	the signal processor's vector unit, 128-byte vectors, each 64-bit value a pair of words	dsp (new class)	emulator
quantum_fabric_dataflow	the first RISC-V core of 32 compute tiles of a dataflow accelerator, two device generations (PCI 1e52:b140, 1e52:401e), driven through the device's library as a PCI endpoint; programs from a new RV32IM encoder (quantum_fabric::rv32) whose listings an independent assembler turns into the same words	dataflow	simulator (open source, built from source at a pinned commit)

Every member: the probe against the CPU's arithmetic, random kernel cases against lanes::run_words, all four pinned certificates, wide circuits against the native simulator, typed refusals, compiled-in kernel mutants each caught, a sealed receipt, and placement beside the CPU reference.

Also: npu::onnx_limb_model writes the neural-processor program in the portable model format (fp16 and int32), with examples/npu_onnx.rs writing a batch of inputs and the exact products they must give; both models pass the format's checker and give every product exactly on its reference runtime.

Found on the way

• The user-mode emulator for the signal processor, before release 11.0, tests a whole predicate register where the processor tests its low bit, in a branch on a predicate written in the same packet. Compiled code relies on the low bit, so one library test fails under such an emulator though the code is right. ci/dsp/predicate_branch.c shows which emulator does which; the workflow builds 11.1.1 from its signed release and runs every suite on it.
• In the pinned standard library, the signal processor's predicate-producing vector intrinsics declare a vector where the code generator expects a predicate, so they do not compile. The kernel uses none: carries and borrows are bit logic on the words.
• The dataflow device's simulator costs nearly the same per clock however many cores are active, so the member spreads each batch over 32 tiles: about 23 times the instructions a second of one core, and the whole device suite in under two minutes per generation.

CI

wai-quantum-npu.yml, wai-quantum-sme.yml, wai-quantum-vector.yml, wai-quantum-dsp.yml and wai-quantum-dataflow.yml, each with the case where the member is absent and says why, and each gated on whether the pull request's own diff touches it.

Follow-up, not in this change

The new members share their host code (gather, range check, certification) by copy; a small row-kernel trait would hold it once.

🤖 Generated with Claude Code

wai-quantum 0.5.1: five more members of the fabric, each certified bit-exact against the CPU reference's pinned corpus digests, and the provenance of each certificate stated (silicon, emulator or simulator). ## Members | Feature | Member | Class | Where it was certified | |---|---|---|---| | `quantum_fabric_npu` | the platform's neural processor: each 32-bit operand as eight 4-bit limbs, every limb product and sum an integer fp16 holds exactly, the host assembling. Credited only where the runtime's compute plan puts every operation on the neural processor; mutants go through the same check | npu | silicon (two machines) | | `quantum_fabric_sme` | the processor's streaming vector mode, 64-bit lanes | cpu-matrix | silicon; emulator | | `quantum_fabric_vector` | the processor's own vector extension: `avx2`, `sve` and `rvv`, the scalable kernels written once for every vector length, the length read back from the unit | cpu | `avx2` silicon; `sve` at 128, 512 and 2048 bits and `rvv` at 128 and 1024 bits under the emulator | | `quantum_fabric_dsp` | the signal processor's vector unit, 128-byte vectors, each 64-bit value a pair of words | dsp (new class) | emulator | | `quantum_fabric_dataflow` | the first RISC-V core of 32 compute tiles of a dataflow accelerator, two device generations (PCI 1e52:b140, 1e52:401e), driven through the device's library as a PCI endpoint; programs from a new RV32IM encoder (`quantum_fabric::rv32`) whose listings an independent assembler turns into the same words | dataflow | simulator (open source, built from source at a pinned commit) | Every member: the probe against the CPU's arithmetic, random kernel cases against `lanes::run_words`, all four pinned certificates, wide circuits against the native simulator, typed refusals, compiled-in kernel mutants each caught, a sealed receipt, and placement beside the CPU reference. Also: `npu::onnx_limb_model` writes the neural-processor program in the portable model format (fp16 and int32), with `examples/npu_onnx.rs` writing a batch of inputs and the exact products they must give; both models pass the format's checker and give every product exactly on its reference runtime. ## Found on the way - The user-mode emulator for the signal processor, before release 11.0, tests a whole predicate register where the processor tests its low bit, in a branch on a predicate written in the same packet. Compiled code relies on the low bit, so one library test fails under such an emulator though the code is right. `ci/dsp/predicate_branch.c` shows which emulator does which; the workflow builds 11.1.1 from its signed release and runs every suite on it. - In the pinned standard library, the signal processor's predicate-producing vector intrinsics declare a vector where the code generator expects a predicate, so they do not compile. The kernel uses none: carries and borrows are bit logic on the words. - The dataflow device's simulator costs nearly the same per clock however many cores are active, so the member spreads each batch over 32 tiles: about 23 times the instructions a second of one core, and the whole device suite in under two minutes per generation. ## CI `wai-quantum-npu.yml`, `wai-quantum-sme.yml`, `wai-quantum-vector.yml`, `wai-quantum-dsp.yml` and `wai-quantum-dataflow.yml`, each with the case where the member is absent and says why, and each gated on whether the pull request's own diff touches it. ## Follow-up, not in this change The new members share their host code (gather, range check, certification) by copy; a small row-kernel trait would hold it once. 🤖 Generated with [Claude Code](https://claude.com/claude-code)

dcharlot added 12 commits 2026-10-15 01:12:08 -04:00

wai-quantum 0.5.1: the neural-processor member ... 015e75fcbe

Co-Authored-By: Claude Opus 5.5 <[email protected]>

npu member: the compute plan and the model cross threads through explicit, lock-guarded handoffs; the qubit limit on every platform ... 3d2e153c16

Co-Authored-By: Claude Opus 5.5 <[email protected]>

wai-quantum 0.5.1: the matrix-extension member (SME), silicon and emulated ... 36b4ddd9ba

Co-Authored-By: Claude Opus 5.5 <[email protected]>

wai-quantum: the limb model in the portable format; f16_of at 2048 ... 437de5d651

npu::onnx_limb_model writes the neural-processor member's program (one
multiply, one sum over the last axis) as an ONNX opset-17 model with fp16
or int32 tensors, and npu::expand_i32 lays out the int32 inputs. The
example npu_onnx writes both models, a batch of inputs and the exact
products they must give, for a neural processor reached through a runtime
that reads that format. Both models pass the full ONNX checker and give
every product of a 16384-pair batch exactly on the reference runtime.

Fix: f16_of(±2048) shifted by 10 - 11 and panicked in a debug build.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

wai-quantum: the signal processor, and its vector unit as a member ... 05fef6cce9

The signal processor (DSP) as a processor: the bit-identity digests (23),
the frame fixtures (2) and the byte-pinning library tests (137) pass for
its Linux target under the user-mode emulator, the standard library built
from source (a tier-3 target).

Emulator releases before 11.0 test a whole predicate register, where the
processor tests its low bit, in a branch on a predicate written in the same
packet. Compiled code relies on the low bit (a predicate from a register's
1, xored with a comparison's 0xff, so 0xfe is "equal"), and one library
test fails under such an emulator though the code is right. The probe
ci/dsp/predicate_branch.c shows it; the workflow builds 11.1.1 from its
release tarball (SHA-256 pinned, signature checked when pinned) and runs
every suite on it.

The member (feature quantum_fabric_dsp, class dsp): the gate's fixed-point
arithmetic in the vector unit's 128-byte vectors, each 64-bit value a pair
of words; the product is the unit's exact 32x32 multiply, and carries and
borrows are bit logic on the words (the standard library's
predicate-producing vector intrinsics do not compile in this release).
Under emulation: 66020 probe pairs agree, 2000 kernel cases match
run_words, all four pinned certificates are reproduced naming the
emulator, circuits up to 20 qubits match native, 3 of 3 mutants are
killed. Elsewhere the member is absent and says why.

Workflow wai-quantum-dsp.yml runs all of it in a pinned container on the
container runner.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

wai-quantum: the CPU vector-unit members (avx2, sve, rvv) ... 47994f302b

The gate's fixed-point arithmetic in the processor's own vector extension,
feature quantum_fabric_vector, class cpu:

- avx2 (x86-64): 256-bit vectors of four 64-bit lanes; the exact signed
  32x32 multiply of each lane's low word, and the 64-bit arithmetic shift
  the unit lacks built from a logical shift and the sign bit;
- sve (aarch64) and rvv (riscv64): one assembly text each for every vector
  length (the length set per pass); the member reads the length from the
  unit and names it in its id and detail.

Each member's id extends the CPU reference's, so with no energy figures
placement keeps the reference. Three kernel mutants per instruction set
are compiled in.

Measured: avx2 on an x86-64 processor; sve at 128, 512 and 2048 bits and
rvv at 128 and 1024 bits under the user-mode emulator. Every leg: 9 of 9
device tests, all four pinned certificates, circuits up to 20 qubits
matching native, 3 of 3 mutants killed, and the length the member read is
the one given. Apple silicon finds no member and says why.

Workflow wai-quantum-vector.yml runs the six legs on the container runner
and the absent case on the macOS runner.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

wai-quantum: the dataflow member, on 32 RISC-V cores of a simulated accelerator ... 29fa40af80

The gate's fixed-point arithmetic on the first core of each of 32 compute
tiles of a dataflow accelerator, two device generations (PCI 1e52:b140 and
1e52:401e), feature quantum_fabric_dataflow, class dataflow.

- quantum_fabric::rv32: an RV32IM encoder and the gate's programs, built as
  machine words and as the listing they encode (the implementation id's
  input). Every 64-bit value is a pair of words: mul/mulh for products,
  sltu for carries and borrows, the arithmetic shift from word shifts. An
  independent assembler turns every listing, conforming and mutant, into the
  same words; examples/rv32_listing writes them for that check.
- The host loads the device's library at run time (WAI_QUANTUM_DATAFLOW_LIB)
  and drives it as a PCI endpoint: reads the ids and the first memory
  window's base from configuration space, opens two windows per tile (its
  memory and its registers), holds the tiles' cores in reset, writes the
  program at the reset address and each tile's parameters and slice of the
  gate's pairs beside it, releases the first cores, clocks the device until
  every tile reports done, and reads the rows back in order.
- Spreading a batch over 32 tiles: the library's cost per clock is mostly
  fixed, so 32 active cores run about 23 times as many instructions a second
  as one.

Measured on the device's open-source simulator, built from source: both
generations 9 of 9 device tests (66020 probe pairs, 2000 kernel cases, all
four pinned certificates, circuits up to 20 qubits matching native, 3 of 3
mutants killed), 75 s and 108 s. Every certificate is labelled simulator.

Workflow wai-quantum-dataflow.yml builds the simulator at a pinned commit,
checks the encoder against the assembler, and runs both generations; the
macOS runner finds no member and says why.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

Merge wai/quantum-0.5.0 (with main) into wai/quantum-npu ... d8ccd14292

Co-Authored-By: Claude Opus 5.5 <[email protected]>

ci: the 0.5.1 member workflows run only when the pull request's own diff touches them ... e5191a6079

Neural processor, matrix extension, signal processor, vector units and the
dataflow device gain the same gate as the other wai-quantum workflows.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

Merge remote-tracking branch 'origin/wai/quantum-0.5.0' into wai/quantum-npu 21217cee73

wai-quantum 0.5.1: review fixes ... 02a45cbd31

- The DSP workflow's x86_64 step looked for "hvx devices" after the rename
  to dsp; it could never pass.
- The neural-processor member's mutants now go through the placement check
  the conforming model does (a mutant placed elsewhere is refused, never
  credited to the processor), and carry their own placement in the detail.
- Its input arrays are written through the strides the runtime gives them,
  as its outputs are read.
- Its compiled model is kept per model text and system build and reused,
  instead of recompiled per process and left in the temp directory; the
  source file is removed after compiling.
- Its per-pair arithmetic allocates nothing (an array, and a lazy error).
- The matrix-extension kernels declare the predicate registers they write.
- A dataflow core that runs past its clock budget is a timeout, which may
  fall back to another member, not a defect.
- The encoder's check against the assembler now covers the programs the
  device runs: the member's own layout, and every mutant's rows and probe.

Verified: neural processor 9/9 on the M3 Ultra twice over one cache (both
mutants placed and killed; one compiled model per text, nothing left in the
temp directory); matrix extension 9/9 on M4 Max silicon; all seven device
programs identical under the independent assembler.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

Merge main (with wai-quantum 0.5.0) into wai/quantum-npu ... 0b1b5134ad

Co-Authored-By: Claude Opus 5.5 <[email protected]>

dcharlot added 1 commit 2026-10-15 01:52:05 -04:00

scripts: no pipe into grep -q under pipefail ... e2392f920a

`printf ... | grep -q` under `set -o pipefail` reports no match when grep
exits at its first match while printf is still writing: printf dies of
SIGPIPE and the pipeline's status is 141. The tests-in-CI self-test failed
that way on the repository checks job (main shows the same job red on one
commit and green on its neighbours), and check-lockfiles.sh classifies
cargo's message the same way, so a timing accident could misread it.
Each now reads a here-string, with nothing to break.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

dcharlot added 1 commit 2026-10-15 09:20:15 -04:00

ci: the signal-processor workflow's emulator variables are not QEMU_* ... 43cead017e

qemu-user reads every QEMU_<option> environment variable as that option,
and QEMU_VERSION is -version: with the workflow's QEMU_VERSION=11.1.1 set,
the emulator printed its version and exited 0 without running anything.
So the bit-identity step found no test results and failed, and the
emulator check before it (the predicate-branch probe) passed without
having run. Reproduced: QEMU_VERSION=11.1.1 qemu-hexagon-11.1.1
/does/not/exist prints the version and exits 0.

The variables are HEXAGON_EMULATOR_VERSION and HEXAGON_EMULATOR_SHA256
now, and the probe's check requires the probe's own statement ("this
emulator branches on the low bit"), so an emulator that runs nothing
fails it.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

dcharlot added 1 commit 2026-10-15 09:57:59 -04:00

Merge remote-tracking branch 'origin/main' into wai/quantum-npu ... 749c429a23

# Conflicts:
#	wai/CHANGELOG.md

dcharlot merged commit ca79392a60 into main 2026-10-15 10:08:35 -04:00

dcharlot referenced this pull request from a commit 2026-10-15 10:08:36 -04:00

Merge pull request 'wai-quantum 0.5.1: neural-processor, matrix-extension, vector-unit, signal-processor and dataflow members' (#263) from wai/quantum-npu into main

dcharlot referenced this pull request from a commit 2026-10-15 10:42:27 -04:00

Merge origin/main (at ca79392a, with #264, #265 and #263) into wai/d2c-m4

dcharlot referenced this pull request 2026-10-15 10:42:30 -04:00

wai-ops: wai.neural.int_hyper and the wai.video.int_hyper keyframe decode through the integer operator set, goldens unchanged (D2c, M4) #267

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