wai-quantum-landscape-fpga: an FPGA board as an open reference member of wai.quantum.landscape/1 #677

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dcharlot merged 16 commits from wai/quantum-landscape-fpga into main 2026-11-07 03:46:41 -05:00

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2026-11-07

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Merge main into wai/quantum-landscape-fpga ...

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-07 03:36:39 -05:00

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wai-quantum-landscape-fpga: held to the grown conformance set, and what it cannot hold said ...

Main's set now holds settle cases to 1,000 cells, chains to 1,024 cells, sampled fields to
2^31 - 1 and a battery workload whose uncertain fields span 135,000, and a member may decline only
fields above 2^31 - 1. The member declines that and nothing else (takes). What the 64-cell engine
cannot hold it refuses with a sentence; member::beyond says why, and the checks hold the board to
the reference's bits on every case it holds and to a refusal on every case it does not. On the
model: 21/21 settle cases and 227/227 chains held, 13 cases refused, so the host certifies both
kernels uncertified under the current set. The README, the changelog and CI say so; the board
was certified bit-exact under the set of 2026-11-06, when its measurements were taken. The build
record carries the testbenches' results on the new session, in Icarus Verilog and xsim alike.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-07 03:36:31 -05:00

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Merge main into wai/quantum-landscape-fpga ...

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-07 03:22:23 -05:00

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wai-quantum-landscape-fpga: the review of #677 answered ...

The lock and reloads. load takes the board lock before it reconfigures, and the session check sees
other runs of this tool and its scripts (their own parents excepted), so a reload waits for the job
that holds the board. The scripts do not hold the lock across the steps they run. A reload of the
same design, which passes the signature and the ID, is seen by the engine's uptime counter and its
reset BOUND register: the engine checks both before it takes a workload or a table as loaded and
after every job, and refuses a result read across a reload. A batch that comes back short, and a
sampled chain whose sweep count is wrong, are refused.

The AXI port. It checks the port's write width as well as its read width; it fills a result page
with the illegal cell pair before a write-back and refuses a result still holding it; it refuses a
transfer whose page moved. It is written against two traits, so a software link tests it off the
board: the guard, the DMA, the sequencer's count, the write-back's layout, dropped accesses.

Tests. lowered_settle's five cases and 300 random workloads with fields to 2^40 against the
reference; the joint test counts against the chains requested and checks the control's cell family.
CI gates on the change, requires tests to run, denies clippy warnings, certifies the model member,
runs a job on it, builds on linux-arm64, and replays both testbenches in Icarus Verilog
(scripts/run_tb.sh). The names check reads .v, .tcl, .xdc and .dat files.

The build. The tool version and each block's version are enforced; the multi-core build refuses the
AXI link. The documents. The latency table says how each row was timed; the engine's share of a
chain is its own clock count; the sampling energy carries its error and its floor; the known answer
is placed in time; the step response is reported; derived figures are marked; the scope of the
meter, the guard's window and the DMA's locked pages are stated; provenance says what the private
code declared; old names are gone; the build and simulator results have a raw record.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-07 03:22:22 -05:00

2026-11-06

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Merge main into wai/quantum-landscape-fpga: #664 has landed ...

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 23:40:25 -05:00

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wai-quantum-landscape-fpga: the board's measurements of rtl version 2, on both links ...

The class campaign on the EMIO build, the checks on it and on both AXI builds, the joint-statistics
test as registered, the processor-to-logic latency, and the power checks of the AXI builds against
the EMIO classes. One of the two nulls failed; the README says what that leaves unclaimed.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 13:57:26 -05:00

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wai-quantum-landscape-fpga: the link meets the board as it boots, and results go back by DMA ...

The processor's master and high-performance ports boot at 128 bits and loading a bitstream does not
change them, so the AXI build meets them with width converters and writes no processor register;
ps-ports reads them, and the host touches no AXI address if they differ. The registers move to
M_AXI_HPM0_FPD at 0xA000_0000, a port designs on this board have already used. A write master sends
a batch's results to DDR, a page at a time, and the testbench checks every word it writes. Writes are
now timed to their response. The class campaign's logs are added.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 10:30:14 -05:00

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wai-quantum-landscape-fpga: pre-register the final AXI build's power check ...

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 10:29:59 -05:00

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wai-quantum-landscape-fpga: pre-register a repeat of the null that failed ...

Co-Authored-By: Claude Opus 5.5 <[email protected]>

ee85a21415

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2026-11-06 10:03:06 -05:00

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wai-quantum-landscape-fpga: read the processor's port widths before the first AXI access ...

The AXI build assumes the low-power-domain master at 32 bits and the high-performance port reading
64 bits a beat, as the board's boot sets them; a different width would put data on the wrong byte
lanes. The host reads both (ps-ports), touches no AXI address if the master's width differs, and
falls back to plain writes if the port's does. The sampled cells of the conformance check vary in
cost and temperature.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 08:37:30 -05:00

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Merge wai/quantum-landscape-emulator (#664) into wai/quantum-landscape-fpga: the host certifies the board, and the board runs any schedule ...

The member trait now takes a schedule of temperatures and says nothing of its own parity. The
board runs each run of sweeps above 0 as sampled segments and each run at 0 in its T0 mode, sweep
k drawing from k*n + 1 whatever came before it, and a sweep at 0 right after sampled sweeps is the
engine's final sweep. Fields and a cost beyond the engine's registers are mapped, for sweeps at 0,
to ones that put every threshold on the same side of every coupling sum a cell can see, so the
settle is the same bit for bit. The checks follow the new set: the settle and chain cases, the cut
points, the statistical battery with the all-at-once control it must catch, and the jobs.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 08:24:09 -05:00

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wai-quantum-landscape-fpga: an AXI link, and the sample kernel held to its exact joint law ...

The engine gets a second link to the processor (rtl/landscape_axi.v): its registers on an AXI-Lite
port, bulk loads (couplings, fields, cut-point tables, chain starts) as write lists the link reads
from DDR by DMA, and a sequencer that runs a batch of up to 256 chains in fabric, start to result,
with nothing from the processor between them. The link answers every access within a few clocks
whatever the engine is doing, and the host reads a signature over EMIO before every AXI access, so
a design replaced by another session is caught before an access could go unanswered.

The host runs a job's chains as one batch, segment by segment, every chain starting a segment with
its draw counter at the draw the reference takes next. A testbench drives the link over AXI-Lite and
its DMA from a memory model and checks every read against the register-level model.

src/exact.rs holds the sample kernel to the exact law of the whole state, enumerated over every
state of small workloads, not only to per-cell frequencies, with a control that has the right
marginals and independent cells and must be rejected. src/latency.rs times the processor-to-logic
accesses on the board. The session check no longer mistakes its own parent process for another
session.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 08:16:09 -05:00

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wai-quantum-landscape-fpga: pre-register the joint-statistics test and the AXI build's power check ...

Both written before either has run on the board.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 08:06:57 -05:00

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Merge wai/quantum-landscape-emulator (#664) into wai/quantum-landscape-fpga: the label names no product ...

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 03:05:26 -05:00

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wai-quantum-landscape-fpga: named for what it is, with its README, provenance, workflow and first measurements ...

The crate is wai-quantum-landscape-fpga, beside the fabric's simulated FPGA member, which has its own
workflow. The README gives the board and part as data, what the design does and refuses, what it
takes to build, the build and load steps, the checks and the power protocol. No bitstream is
distributed: the vendor tool's licence limits a bitstream holding its components to that vendor's
devices, which Apache-2.0 does not carry, so the README gives the build and the sha256 of the
bitstream measured.

measurements/2026-11-05 holds the first version's raw power logs and the predictions committed
before them, unchanged. The workflow runs the unit tests and every check against the model of the
logic on each change.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 03:05:19 -05:00

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wai-quantum-fpga: an FPGA board as a member of wai.quantum.landscape/1, and its power prediction ...

The engine (rtl/) runs the settle and sample kernels of the energy-landscape job for up to 64
three-state cells in programmable logic. Couplings, fields, the cost and the cut-point table are
registers the host writes. The sample kernel takes the reference's draws: the engine counts
chain + j * 0x9E3779B97F4A7C15 and runs SplitMix64's mix in a nine-stage pipeline, and compares the
top 53 bits with cut points the host computes with the reference's cuts(), so the logic needs no
exponential. A field outside the table's window takes the threshold, and the host puts the window
over every field whose draw is not certain, or refuses the job.

The host (src/) implements wai_quantum::quantum_landscape::member::Member for the board, earns its
parity by running the conformance set's settle and chains vectors on the device at start, and
answers jobs through job::call_on, sealed. src/model.rs models the logic at the register port; the
testbench (tb/) replays a session recorded from it against the RTL and compares every read.

On the board at 100 MHz: the settle and chains vectors bit for bit, so both kernels are bit-exact;
the cell and coupled frequency tests with every draw equal to the reference's; the jobs vectors
14/14; every worked example over 200 seeds at its own temperature and at 0, answer for answer
identical to the CPU reference.

measurements/2026-11-06/PREDICTION.txt is committed before the power measurement it predicts.

Co-Authored-By: Claude Opus 5.5 <[email protected]>

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2026-11-06 03:01:36 -05:00