d4867b1b83
The lock and reloads. load takes the board lock before it reconfigures, and the session check sees other runs of this tool and its scripts (their own parents excepted), so a reload waits for the job that holds the board. The scripts do not hold the lock across the steps they run. A reload of the same design, which passes the signature and the ID, is seen by the engine's uptime counter and its reset BOUND register: the engine checks both before it takes a workload or a table as loaded and after every job, and refuses a result read across a reload. A batch that comes back short, and a sampled chain whose sweep count is wrong, are refused. The AXI port. It checks the port's write width as well as its read width; it fills a result page with the illegal cell pair before a write-back and refuses a result still holding it; it refuses a transfer whose page moved. It is written against two traits, so a software link tests it off the board: the guard, the DMA, the sequencer's count, the write-back's layout, dropped accesses. Tests. lowered_settle's five cases and 300 random workloads with fields to 2^40 against the reference; the joint test counts against the chains requested and checks the control's cell family. CI gates on the change, requires tests to run, denies clippy warnings, certifies the model member, runs a job on it, builds on linux-arm64, and replays both testbenches in Icarus Verilog (scripts/run_tb.sh). The names check reads .v, .tcl, .xdc and .dat files. The build. The tool version and each block's version are enforced; the multi-core build refuses the AXI link. The documents. The latency table says how each row was timed; the engine's share of a chain is its own clock count; the sampling energy carries its error and its floor; the known answer is placed in time; the step response is reported; derived figures are marked; the scope of the meter, the guard's window and the DMA's locked pages are stated; provenance says what the private code declared; old names are gone; the build and simulator results have a raw record. Co-Authored-By: Claude Opus 5.5 <[email protected]>
1.7 KiB
1.7 KiB
2026-11-06: rtl version 2, on the EMIO link and on the AXI link
Raw output as the board wrote it. Board-level, one board, one meter. The *.txt files at the top
are the predictions and pre-registrations, each committed before the measurement it covers.
| file | what |
|---|---|
PREDICTION.txt |
the class predictions for rtl version 2 |
first-attempt/ |
08:01 UTC on the EMIO build: the run/halt step and the known-answer vehicle; then the reload refused (the session check matched its own parent process, since fixed) |
emio-classes/ |
12:39 to 14:55 UTC on the EMIO build (sha256 feea5015...): step, null, settle, sampling, idle, the settle job at 50 MHz |
emio-checks/ |
the same build afterwards: conformance, agreement, latency, throughput, the processor's port widths |
AXI-PREDICTION.txt |
committed at 13:06 UTC, during the class campaign and before its null had finished, and before the AXI build was metered |
NULL-REPEAT.txt |
committed at 15:03 UTC, after the class campaign ended and its null had failed, before the AXI build was metered |
axi-first/ |
the first AXI build (sha256 3d84dbd3..., results read back by register reads): checks, then power/ (the settle check and the repeated null) |
JOINT-PREREG.txt |
the joint-statistics test, registered before its first board run (axi-first/joint.txt) |
AXI-FINAL-PREDICTION.txt, axi-final/ |
the final AXI build (sha256 bb825055..., results written back by DMA): checks, then power/ (the settle check) |
build.txt |
the builds: tool and block versions, sizes, timing, each bitstream's sha256, and the testbenches' results |
Summarise a meter log with wai-quantum-landscape-fpga analyze <file> or
python3 scripts/power_tables.py <files>.