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Main's set now holds settle cases to 1,000 cells, chains to 1,024 cells, sampled fields to 2^31 - 1 and a battery workload whose uncertain fields span 135,000, and a member may decline only fields above 2^31 - 1. The member declines that and nothing else (takes). What the 64-cell engine cannot hold it refuses with a sentence; member::beyond says why, and the checks hold the board to the reference's bits on every case it holds and to a refusal on every case it does not. On the model: 21/21 settle cases and 227/227 chains held, 13 cases refused, so the host certifies both kernels uncertified under the current set. The README, the changelog and CI say so; the board was certified bit-exact under the set of 2026-11-06, when its measurements were taken. The build record carries the testbenches' results on the new session, in Icarus Verilog and xsim alike. Co-Authored-By: Claude Opus 5.5 <[email protected]>
33 lines
2.8 KiB
Text
33 lines
2.8 KiB
Text
The builds measured on 2026-11-06, and the testbenches' results. Copied from the tool's reports and
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logs (its utilisation and timing reports, its build log, sha256sum), the lines that bear on the
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README, without the reports' headers.
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TOOL
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Vivado v2026.1 (lin64), build 6511674. Blocks: zynq_ultra_ps_e 3.5; in the AXI builds also
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axi_dwidth_converter 2.1 (twice) and axi_protocol_converter 2.1.
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The AXI builds ran with JOBS 1, general.maxThreads 2, under a 10 GB memory cap; the tool's own
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peak, as its log reports it, was 5,140 MB. An earlier attempt with JOBS 2 and no cap, on a 15 GB
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machine shared with other builds, ran the machine out of memory.
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BUILDS (part xck26-sfvc784-2LV-c, 100 MHz)
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build sha256 of the .bit.bin LUTs registers BRAM tiles URAM DSP WNS WHS
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AXI, final (write-back) bb82505526e33403073924373a64d3519394344e9bf6d0193634c157e42b6dfb 28145 (24.03%) 13773 4 4 20 0.993 ns 0.012 ns
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AXI, first (no write-back) 3d84dbd355c9552c7593d3d5aa823284a4941acd25e5f3b7c92d5c0bc36ee441 27666 (23.62%) 13220 4 4 20 0.698 ns 0.012 ns
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EMIO, one engine feea5015b2f8d85049fd48bcc66493a411d551326365f67b1db2ae65ec00074c 25539 (21.81%) 11121 0 4 20 0.294 ns 0.069 ns
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EMIO, four engines 2a73f02b5a6097bd251962b7d91f5ca368180db162941465aa32129130b06b09 80927 (69.10%) 44355 0 16 80 0.441 ns 0.010 ns
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(four engines: 13,925 of 14,640 slices, 95.12%; not loaded on the board this day)
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All four: 0 failing endpoints, setup and hold. The AXI builds report one critical warning, a
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false-path constraint for the EMIO port's synchroniser that finds no cell in them.
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TESTBENCHES, on the scripts gen-tb records from this commit's model (sha256 of each script)
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EMIO landscape_tb.script 4fb49e25f794849db750d688755ef452f05fb9146fd0cb016ad0b533dee5205e
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Icarus Verilog 13.0: TB DONE: 174345 lines, 2668 checked reads, 0 mismatches, sim time 26571197000
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xsim v2026.1: TB DONE: 174345 lines, 2668 checked reads, 0 mismatches, sim time 26571197000
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AXI landscape_axi_tb.script 927b463dd40b9a3535fe77a770656415b58ce2dae33a93bf3299b3ab5252fc5c
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171 write lists, 50 batches, 50 write-backs
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Icarus Verilog 13.0: TB DONE: 175830 lines, 4464 checked reads, 0 mismatches, sim time 6878426000
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xsim v2026.1: TB DONE: 175830 lines, 4464 checked reads, 0 mismatches, sim time 6878426000
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A flipped expected word in a write-back's results (xsim, the earlier script):
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MISMATCH line 1231: written back chain 0 word 2 got 00000000 want f0000000
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The RTL the scripts ran against is the final AXI build's: no file under rtl/ that it is built
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from has changed since that build but for comments.
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