c2db9d17d1
The processor's master and high-performance ports boot at 128 bits and loading a bitstream does not change them, so the AXI build meets them with width converters and writes no processor register; ps-ports reads them, and the host touches no AXI address if they differ. The registers move to M_AXI_HPM0_FPD at 0xA000_0000, a port designs on this board have already used. A write master sends a batch's results to DDR, a page at a time, and the testbench checks every word it writes. Writes are now timed to their response. The class campaign's logs are added. Co-Authored-By: Claude Opus 5.5 <[email protected]>
65 lines
4.1 KiB
Verilog
65 lines
4.1 KiB
Verilog
// SPDX-License-Identifier: Apache-2.0
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// KV260 top for the AXI link: the processing system gives the clock, an AXI-Lite master (its
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// full-power-domain master port, through a width and a protocol converter), a high-performance slave port
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// into DDR (through a width converter), and the EMIO lines. See landscape.tcl for why the widths
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// are what they are. The reset is the fabric's own: a counter that holds the link's control in
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// reset for 128 clocks after configuration, so the design does not depend on the state the
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// processor's PL reset line was left in.
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`timescale 1ns/1ps
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module design_top();
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wire pl_clk0;
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reg [7:0] por = 8'd0;
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always @(posedge pl_clk0) if (!por[7]) por <= por + 8'd1;
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wire rstn = por[7];
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wire [39:0] l_awaddr, l_araddr;
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wire [31:0] l_wdata, l_rdata;
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wire l_awvalid, l_awready, l_wvalid, l_wready, l_bvalid, l_bready, l_arvalid, l_arready, l_rvalid, l_rready;
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wire [1:0] l_bresp, l_rresp;
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wire [3:0] l_wstrb;
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wire [2:0] l_awprot, l_arprot;
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wire [48:0] d_araddr;
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wire [7:0] d_arlen;
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wire [2:0] d_arsize, d_arprot;
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wire [1:0] d_arburst, d_rresp;
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wire [3:0] d_arcache;
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wire d_arvalid, d_arready, d_rlast, d_rvalid, d_rready;
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wire [48:0] d_awaddr;
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wire [7:0] d_awlen, d_wstrb;
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wire [2:0] d_awsize, d_awprot;
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wire [1:0] d_awburst, d_bresp;
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wire [3:0] d_awcache;
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wire [63:0] d_wdata;
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wire d_awvalid, d_awready, d_wlast, d_wvalid, d_wready, d_bvalid, d_bready;
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wire [63:0] d_rdata;
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wire [94:0] emio_o, emio_i;
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sys_wrapper ps_i (
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.pl_clk0(pl_clk0), .aresetn(rstn), .emio_o(emio_o), .emio_i(emio_i),
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.LITE_awaddr(l_awaddr), .LITE_awprot(l_awprot), .LITE_awvalid(l_awvalid), .LITE_awready(l_awready),
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.LITE_wdata(l_wdata), .LITE_wstrb(l_wstrb), .LITE_wvalid(l_wvalid), .LITE_wready(l_wready),
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.LITE_bresp(l_bresp), .LITE_bvalid(l_bvalid), .LITE_bready(l_bready),
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.LITE_araddr(l_araddr), .LITE_arprot(l_arprot), .LITE_arvalid(l_arvalid), .LITE_arready(l_arready),
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.LITE_rdata(l_rdata), .LITE_rresp(l_rresp), .LITE_rvalid(l_rvalid), .LITE_rready(l_rready),
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.DMA_araddr(d_araddr), .DMA_arlen(d_arlen), .DMA_arsize(d_arsize), .DMA_arburst(d_arburst),
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.DMA_arcache(d_arcache), .DMA_arprot(d_arprot), .DMA_arvalid(d_arvalid), .DMA_arready(d_arready),
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.DMA_arlock(1'b0), .DMA_arqos(4'd0), .DMA_arregion(4'd0),
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.DMA_rdata(d_rdata), .DMA_rresp(d_rresp), .DMA_rlast(d_rlast), .DMA_rvalid(d_rvalid), .DMA_rready(d_rready),
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.DMA_awaddr(d_awaddr), .DMA_awlen(d_awlen), .DMA_awsize(d_awsize), .DMA_awburst(d_awburst), .DMA_awcache(d_awcache),
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.DMA_awprot(d_awprot), .DMA_awvalid(d_awvalid), .DMA_awready(d_awready), .DMA_awlock(1'b0), .DMA_awqos(4'd0), .DMA_awregion(4'd0),
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.DMA_wdata(d_wdata), .DMA_wstrb(d_wstrb), .DMA_wlast(d_wlast), .DMA_wvalid(d_wvalid), .DMA_wready(d_wready),
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.DMA_bresp(d_bresp), .DMA_bvalid(d_bvalid), .DMA_bready(d_bready)
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);
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landscape_axi u (
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.clk(pl_clk0), .rstn(rstn),
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.s_awaddr(l_awaddr[31:0]), .s_awvalid(l_awvalid), .s_awready(l_awready), .s_wdata(l_wdata), .s_wvalid(l_wvalid),
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.s_wready(l_wready), .s_bresp(l_bresp), .s_bvalid(l_bvalid), .s_bready(l_bready),
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.s_araddr(l_araddr[31:0]), .s_arvalid(l_arvalid), .s_arready(l_arready), .s_rdata(l_rdata), .s_rresp(l_rresp),
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.s_rvalid(l_rvalid), .s_rready(l_rready),
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.m_araddr(d_araddr), .m_arlen(d_arlen), .m_arsize(d_arsize), .m_arburst(d_arburst), .m_arcache(d_arcache),
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.m_arprot(d_arprot), .m_arvalid(d_arvalid), .m_arready(d_arready), .m_rdata(d_rdata), .m_rresp(d_rresp),
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.m_rlast(d_rlast), .m_rvalid(d_rvalid), .m_rready(d_rready),
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.m_awaddr(d_awaddr), .m_awlen(d_awlen), .m_awsize(d_awsize), .m_awburst(d_awburst), .m_awcache(d_awcache),
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.m_awprot(d_awprot), .m_awvalid(d_awvalid), .m_awready(d_awready), .m_wdata(d_wdata), .m_wstrb(d_wstrb),
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.m_wlast(d_wlast), .m_wvalid(d_wvalid), .m_wready(d_wready), .m_bresp(d_bresp), .m_bvalid(d_bvalid), .m_bready(d_bready),
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.emio_i(emio_i)
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);
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endmodule
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